riscv/rocket-chip
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238 Commits

Author SHA1 Message Date
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Andrew Waterman
fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Andrew Waterman
44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman
4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Megan Wachs
bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00
Andrew Waterman
05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Andrew Waterman
d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
a2a3346e73
 2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Megan Wachs
08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) 
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
 2017-03-27 02:45:37 -07:00
Andrew Waterman
5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Henry Cook
996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00
Andrew Waterman
17b1ee3037 Default to 8 PMPs; support 0 PMPs 2017-03-24 16:39:52 -07:00
Andrew Waterman
97006ab396 Don't modulate PMP privilege on passsthrough when !usingVM 2017-03-24 16:39:52 -07:00
Andrew Waterman
3f0d2fe826 Instantiate PTW unconditionally 
This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
30415215b8 Don't check for exceptions on ScratchpadSlavePort accesses 2017-03-24 16:39:52 -07:00
Andrew Waterman
ccd5bc9a91 Improve QoR of PMP homogeneity checker 2017-03-24 16:39:52 -07:00
Andrew Waterman
e9cadf29d2 Improve DCache MMIO QoR 
No need to store the cmd field.  From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
fb6498f2c3 Use Reg(Vec) instead of Seq(Reg) for DCache MMIO 2017-03-24 16:39:52 -07:00
Andrew Waterman
0538dc77ce For D$, use source 0 through N-1 for MMIO, not 1 through N 
This makes the code a bit cleaner.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
3951e57789 Force each TLB entry into its own clock-gate group 
This ameliorates a PMP critical path.

I can't figure out how to do this without asUInt/asTypeOf.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
8d7f1d777e Fix an embarrassing typo in the PMPHeterogeneityChecker 2017-03-24 16:39:52 -07:00
Andrew Waterman
10c39cb8d6 Disable mprv in D-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman
d3bda9574c Put page homogeneity checker in PMP 
Avoids redundancy between ITLB and DTLB
 2017-03-24 16:39:52 -07:00
Andrew Waterman
9e05200e51 Don't require that PMP ranges be aligned to access size 
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
29e67279ba add comments 2017-03-24 16:39:52 -07:00
Andrew Waterman
4c8be13a4d Improve homogeneity circuit QoR 2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132 mideleg/medeleg not present without less-privileged traps 2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5 Share PMP mask gen between I$ and D$ 2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf More WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422 Flush pipeline from WB stage, not MEM 
Fixes sptbr write -> instruction translation hazard.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab Retime PTW response valid bits 
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c Default TLB size = 32 
@davidbiancolin
 2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316 Get TLB permission checks off D$ clock gating critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4 Expose MXR to S-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329 PUM -> SUM 2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23 Simplify interrupt-stack discipline 
f2ed45b179
 2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2 Mitigate some more PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman
7484f27ed3 Don't gate exception-cause pipeline registers separately 
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
 2017-03-24 16:39:52 -07:00