Leway Colin
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87d909e996
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Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563)
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2017-02-24 10:37:26 -08:00 |
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Wesley W. Terpstra
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e5af59db68
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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Wesley W. Terpstra
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b7963eca4e
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copyright: ran scripts/modify-copyright
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2016-11-27 22:15:43 -08:00 |
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Wesley W. Terpstra
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37a3c22639
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Andrew Waterman
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5828e6042e
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Work around https://github.com/ucb-bar/firrtl/issues/299
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2016-09-14 11:47:10 -07:00 |
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Howard Mao
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1882241493
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move junctions utils into top-level utils package
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2016-09-13 20:47:04 -07:00 |
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Henry Cook
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7dd4492abb
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First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
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2016-09-13 20:30:14 -07:00 |
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Howard Mao
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7b20609d4d
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reorganize moving non-submodule packages into src/main/scala
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2016-08-19 13:45:23 -07:00 |
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