566 lines
22 KiB
Scala
566 lines
22 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package junctions
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import Chisel._
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import config._
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import unittest.UnitTest
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import util.ParameterizedBundle
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object HastiConstants
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{
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// Values for htrans
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val SZ_HTRANS = 2
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val HTRANS_IDLE = UInt(0, SZ_HTRANS) // No transfer requested, not in a burst
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val HTRANS_BUSY = UInt(1, SZ_HTRANS) // No transfer requested, in a burst
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val HTRANS_NONSEQ = UInt(2, SZ_HTRANS) // First (potentially only) request in a burst
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val HTRANS_SEQ = UInt(3, SZ_HTRANS) // Following requests in a burst
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// Values for hburst
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val SZ_HBURST = 3
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val HBURST_SINGLE = UInt(0, SZ_HBURST) // Single access (no burst)
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val HBURST_INCR = UInt(1, SZ_HBURST) // Incrementing burst of arbitrary length, not crossing 1KB
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val HBURST_WRAP4 = UInt(2, SZ_HBURST) // 4-beat wrapping burst
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val HBURST_INCR4 = UInt(3, SZ_HBURST) // 4-beat incrementing burst
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val HBURST_WRAP8 = UInt(4, SZ_HBURST) // 8-beat wrapping burst
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val HBURST_INCR8 = UInt(5, SZ_HBURST) // 8-beat incrementing burst
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val HBURST_WRAP16 = UInt(6, SZ_HBURST) // 16-beat wrapping burst
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val HBURST_INCR16 = UInt(7, SZ_HBURST) // 16-beat incrementing burst
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// Values for hresp
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val SZ_HRESP = 1
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val HRESP_OKAY = UInt(0, SZ_HRESP)
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val HRESP_ERROR = UInt(1, SZ_HRESP)
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// Values for hsize are identical to TileLink MT_SZ
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// ie: 8*2^SZ_HSIZE bit transfers
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val SZ_HSIZE = 3
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// Values for hprot (a bitmask)
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val SZ_HPROT = 4
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def HPROT_DATA = UInt("b0001") // Data access or Opcode fetch
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def HPROT_PRIVILEGED = UInt("b0010") // Privileged or User access
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def HPROT_BUFFERABLE = UInt("b0100") // Bufferable or non-bufferable
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def HPROT_CACHEABLE = UInt("b1000") // Cacheable or non-cacheable
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def dgate(valid: Bool, b: UInt) = Fill(b.getWidth, valid) & b
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}
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import HastiConstants._
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case class HastiParameters(dataBits: Int, addrBits: Int)
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case object HastiId extends Field[String]
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case class HastiKey(id: String) extends Field[HastiParameters]
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trait HasHastiParameters {
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implicit val p: Parameters
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val hastiParams = p(HastiKey(p(HastiId)))
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val hastiAddrBits = hastiParams.addrBits
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val hastiDataBits = hastiParams.dataBits
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val hastiDataBytes = hastiDataBits/8
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val hastiAlignment = log2Ceil(hastiDataBytes)
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}
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abstract class HastiModule(implicit val p: Parameters) extends Module
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with HasHastiParameters
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abstract class HastiBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasHastiParameters
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class HastiMasterIO(implicit p: Parameters) extends HastiBundle()(p) {
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val htrans = UInt(OUTPUT, SZ_HTRANS)
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val hmastlock = Bool(OUTPUT)
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val haddr = UInt(OUTPUT, hastiAddrBits)
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val hwrite = Bool(OUTPUT)
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val hburst = UInt(OUTPUT, SZ_HBURST)
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val hsize = UInt(OUTPUT, SZ_HSIZE)
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val hprot = UInt(OUTPUT, SZ_HPROT)
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val hwdata = Bits(OUTPUT, hastiDataBits)
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val hrdata = Bits(INPUT, hastiDataBits)
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val hready = Bool(INPUT)
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val hresp = UInt(INPUT, SZ_HRESP)
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def isNSeq(dummy:Int=0) = htrans === HTRANS_NONSEQ // SEQ does not start a NEW request
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def isHold(dummy:Int=0) = htrans === HTRANS_BUSY || htrans === HTRANS_SEQ
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def isIdle(dummy:Int=0) = htrans === HTRANS_IDLE || htrans === HTRANS_BUSY
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}
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class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
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val htrans = UInt(INPUT, SZ_HTRANS)
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val hmastlock = Bool(INPUT)
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val haddr = UInt(INPUT, hastiAddrBits)
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val hwrite = Bool(INPUT)
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val hburst = UInt(INPUT, SZ_HBURST)
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val hsize = UInt(INPUT, SZ_HSIZE)
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val hprot = UInt(INPUT, SZ_HPROT)
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val hwdata = Bits(INPUT, hastiDataBits)
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val hrdata = Bits(OUTPUT, hastiDataBits)
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val hsel = Bool(INPUT)
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val hready = Bool(OUTPUT)
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val hresp = UInt(OUTPUT, SZ_HRESP)
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}
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/* A diverted master is told hready when his address phase goes nowhere.
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* In this case, we buffer his address phase request and replay it later.
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* NOTE: this must optimize to nothing when divert is constantly false.
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*/
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class MasterDiversion(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val in = (new HastiMasterIO).flip
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val out = (new HastiMasterIO)
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val divert = Bool(INPUT)
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}
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val full = Reg(init = Bool(false))
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val buffer = Reg(new HastiMasterIO)
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when (io.out.hready) {
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full := Bool(false)
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}
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when (io.divert) {
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full := Bool(true)
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buffer := io.in
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}
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// If the master is diverted, he must also have been told hready
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assert (!io.divert || io.in.hready,
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"Diverted but not ready");
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// Replay the request we diverted
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io.out.htrans := Mux(full, buffer.htrans, io.in.htrans)
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io.out.hmastlock := Mux(full, buffer.hmastlock, io.in.hmastlock)
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io.out.haddr := Mux(full, buffer.haddr, io.in.haddr)
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io.out.hwrite := Mux(full, buffer.hwrite, io.in.hwrite)
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io.out.hburst := Mux(full, buffer.hburst, io.in.hburst)
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io.out.hsize := Mux(full, buffer.hsize, io.in.hsize)
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io.out.hprot := Mux(full, buffer.hprot, io.in.hprot)
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io.out.hwdata := Mux(full, buffer.hwdata, io.in.hwdata)
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// Pass slave response back
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io.in.hrdata := io.out.hrdata
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io.in.hresp := io.out.hresp
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io.in.hready := io.out.hready && !full // Block master while we steal his address phase
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}
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/* Masters with lower index have priority over higher index masters.
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* However, a lower priority master will retain control of a slave when EITHER:
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* 1. a burst is in progress (switching slaves mid-burst violates AHB-lite at slave)
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* 2. a transfer was waited (the standard forbids changing requests in this case)
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*
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* If a master raises hmastlock, it will be waited until no other master has inflight
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* requests; then, it acquires exclusive control of the crossbar until hmastlock is low.
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*
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* To implement an AHB-lite crossbar, it is important to realize that requests and
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* responses are coupled. Unlike modern bus protocols where the response data has flow
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* control independent of the request data, in AHB-lite, both flow at the same time at
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* the sole discretion of the slave via the hready signal. The address and data are
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* delivered on two back-to-back cycles, the so-called address and data phases.
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*
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* Masters can only be connected to a single slave at a time. If a master had two different
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* slave connections on the address and data phases, there would be two independent hready
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* signals. An AHB-lite slave can assume that data flows when it asserts hready. If the data
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* slave deasserts hready while the address slave asserts hready, the master is put in the
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* impossible position of being in data phase on two slaves at once. For this reason, when
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* a master issues back-to-back accesses to distinct slaves, we inject a pipeline bubble
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* between the two requests to limit the master to just a single slave at a time.
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*
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* Conversely, a slave CAN have two masters attached to it. This is unproblematic, because
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* the only signal which governs data flow is hready. Thus, both masters can be stalled
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* safely by the single slave.
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*/
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class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val masters = Vec(nMasters, new HastiMasterIO).flip
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val slaves = Vec(addressMap.size, new HastiSlaveIO).flip
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}
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val nSlaves = addressMap.size
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// Setup diversions infront of each master
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val diversions = Seq.tabulate(nMasters) { m => Module(new MasterDiversion) }
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(io.masters zip diversions) foreach { case (m, d) => d.io.in <> m }
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// Handy short-hand
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val masters = diversions map (_.io.out)
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val slaves = io.slaves
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// Lock status of the crossbar
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val lockedM = Reg(init = Vec.fill(nMasters)(Bool(false)))
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val isLocked = lockedM.reduce(_ || _)
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// This matrix governs the master-slave connections in the address phase
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// It is indexed by addressPhaseGrantSM(slave)(master)
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// It is guaranteed to have at most one 'true' per column and per row
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val addressPhaseGrantSM = Wire(Vec(nSlaves, Vec(nMasters, Bool())))
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// This matrix governs the master-slave connections in the data phase
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// It is guaranteed to have at most one 'true' per column and per row
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val dataPhaseGrantSM = Reg (init = Vec.fill(nSlaves)(Vec.fill(nMasters)(Bool(false))))
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// This matrix is the union of the address and data phases.
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// It is transposed with respect to the two previous matrices.
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// It is guaranteed to contain at most one 'true' per master row.
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// However, two 'true's per slave column are permitted.
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val unionGrantMS = Vec.tabulate(nMasters) { m => Vec.tabulate(nSlaves) { s =>
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addressPhaseGrantSM(s)(m) || dataPhaseGrantSM(s)(m) } }
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// Confirm the guarantees made above
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def justOnce(v: Vec[Bool]) = v.fold(Bool(false)) { case (p, v) =>
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assert (!p || !v)
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p || v
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}
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addressPhaseGrantSM foreach { s => justOnce(s) }
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unionGrantMS foreach { s => justOnce(s) }
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// Data phase follows address phase whenever the slave is ready
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(slaves zip (dataPhaseGrantSM zip addressPhaseGrantSM)) foreach { case (s, (d, a)) =>
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when (s.hready) { d := a }
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}
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// Record the grant state from the previous cycle; needed in case we hold access
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val priorAddressPhaseGrantSM = RegNext(addressPhaseGrantSM)
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// If a master says BUSY or SEQ, it is in the middle of a burst.
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// In this case, it MUST stay attached to the same slave as before.
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// Otherwise, it would violate the AHB-lite specification as seen by
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// the slave, which is guaranteed a complete burst of the promised length.
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// One case where this matters is preventing preemption of low-prio masters.
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// NOTE: this exposes a slave to bad addresses when a master is buggy
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val holdBurstM = Vec(masters map { _.isHold() })
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// Transform the burst hold requirement from master indexing to slave indexing
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// We use the previous cycle's binding because the master continues the prior burst
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val holdBurstS = Vec(priorAddressPhaseGrantSM map { m => Mux1H(m, holdBurstM) })
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// If a slave says !hready to a request, it must retain the same master next cycle.
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// The AHB-lite specification requires that a waited transfer remain unchanged.
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// If we preempted a waited master, the new master's request could potentially differ.
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val holdBusyS = RegNext(Vec(slaves map { s => !s.hready && s.hsel }))
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// Combine the above two grounds to determine if the slave retains its prior master
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val holdS = Vec((holdBurstS zip holdBusyS) map ({ case (a,b) => a||b }))
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// Determine which master addresses match which slaves
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val matchMS = Vec(masters map { m => Vec(addressMap map { afn => afn(m.haddr) }) })
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// Detect requests to nowhere; we need to allow progress in this case
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val nowhereM = Vec(matchMS map { s => !s.reduce(_ || _) })
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// Detect if we need to inject a pipeline bubble between the master requests.
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// Divert masters already granted a data phase different from next request.
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// NOTE: if only one slave, matchMS is always true => bubble always false
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// => the diversion registers are optimized away as they are unread
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// NOTE: bubble => dataPhase => have an hready signal
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val bubbleM =
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Vec.tabulate(nMasters) { m =>
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Vec.tabulate(nSlaves) { s => dataPhaseGrantSM(s)(m) && !matchMS(m)(s) }
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.reduce(_ || _) }
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// Block any request that requires bus ownership or conflicts with isLocked
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val blockedM =
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Vec((lockedM zip masters) map { case(l, m) => !l && (isLocked || m.hmastlock) })
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// Requested access to slaves from masters (pre-arbitration)
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// NOTE: isNSeq does NOT include SEQ; thus, masters who are midburst do not
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// request access to a new slave. They stay tied to the old and do not get two.
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// NOTE: if a master was waited, it must repeat the same request as last cycle;
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// thus, it will request the same slave and not end up with two (unless buggy).
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val NSeq = masters.map(_.isNSeq())
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val requestSM = Vec.tabulate(nSlaves) { s => Vec.tabulate(nMasters) { m =>
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matchMS(m)(s) && NSeq(m) && !bubbleM(m) && !blockedM(m) } }
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// Select at most one master request per slave (lowest index = highest priority)
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val selectedRequestSM = Vec(requestSM map { m => Vec(PriorityEncoderOH(m)) })
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// Calculate new crossbar interconnect state
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addressPhaseGrantSM := Vec((holdS zip (priorAddressPhaseGrantSM zip selectedRequestSM))
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map { case (h, (p, r)) => Mux(h, p, r) })
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for (m <- 0 until nMasters) {
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// If the master is connected to a slave, the slave determines hready.
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// However, if no slave is connected, for progress report ready anyway, if:
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// bad address (swallow request) OR idle (permit stupid masters to move FSM)
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val autoready = nowhereM(m) || masters(m).isIdle()
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val hready = Mux1H(unionGrantMS(m), slaves.map(_.hready ^ autoready)) ^ autoready
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masters(m).hready := hready
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// If we diverted a master, we need to absorb his address phase to replay later
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diversions(m).io.divert := (bubbleM(m) || blockedM(m)) && NSeq(m) && hready
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}
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// Master muxes (address and data phase are the same)
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(masters zip unionGrantMS) foreach { case (m, g) => {
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m.hrdata := Mux1H(g, slaves.map(_.hrdata))
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m.hresp := Mux1H(g, slaves.map(_.hresp))
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} }
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// Slave address phase muxes
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(slaves zip addressPhaseGrantSM) foreach { case (s, g) => {
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s.htrans := Mux1H(g, masters.map(_.htrans))
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s.haddr := Mux1H(g, masters.map(_.haddr))
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s.hmastlock := isLocked
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s.hwrite := Mux1H(g, masters.map(_.hwrite))
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s.hsize := Mux1H(g, masters.map(_.hsize))
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s.hburst := Mux1H(g, masters.map(_.hburst))
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s.hprot := Mux1H(g, masters.map(_.hprot))
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s.hsel := g.reduce(_ || _)
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} }
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// Slave data phase muxes
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(slaves zip dataPhaseGrantSM) foreach { case (s, g) => {
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s.hwdata := Mux1H(g, masters.map(_.hwdata))
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} }
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// When no master-slave connections are active, a master can take-over the bus
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val canLock = !addressPhaseGrantSM.map({ v => v.reduce(_ || _) }).reduce(_ || _)
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// Lowest index highest priority for lock arbitration
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val reqLock = masters.map(_.hmastlock)
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val winLock = PriorityEncoderOH(reqLock)
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// Lock arbitration
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when (isLocked) {
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lockedM := (lockedM zip reqLock) map { case (a,b) => a && b }
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} .elsewhen (canLock) {
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lockedM := winLock
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}
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}
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class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val master = new HastiMasterIO().flip
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val slaves = Vec(amap.size, new HastiSlaveIO).flip
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}
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val bar = Module(new HastiXbar(1, amap))
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bar.io.masters(0) <> io.master
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bar.io.slaves <> io.slaves
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}
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class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val ins = Vec(n, new HastiSlaveIO)
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val out = new HastiSlaveIO().flip
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}
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val amap = Seq({ (_:UInt) => Bool(true)})
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val bar = Module(new HastiXbar(n, amap))
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io.ins <> bar.io.masters
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io.out <> bar.io.slaves(0)
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}
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class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val in = new HastiSlaveIO
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val out = new HastiMasterIO
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}
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io.out.htrans := Mux(io.in.hsel, io.in.htrans, HTRANS_IDLE)
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io.out.hmastlock := io.in.hmastlock
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io.out.haddr := io.in.haddr
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io.out.hwrite := io.in.hwrite
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io.out.hburst := io.in.hburst
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io.out.hsize := io.in.hsize
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io.out.hprot := io.in.hprot
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io.out.hwdata := io.in.hwdata
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io.in.hrdata := io.out.hrdata
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io.in.hready := io.out.hready
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io.in.hresp := io.out.hresp
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}
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class HastiMasterIONastiIOConverter(implicit p: Parameters) extends HastiModule()(p)
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with HasNastiParameters {
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val io = new Bundle {
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val nasti = new NastiIO().flip
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val hasti = new HastiMasterIO
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}
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require(hastiAddrBits == nastiXAddrBits)
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require(hastiDataBits == nastiXDataBits)
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val r_queue = Module(new Queue(new NastiReadDataChannel, 2, pipe = true))
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val s_idle :: s_read :: s_write :: s_write_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val addr = Reg(UInt(width = hastiAddrBits))
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val id = Reg(UInt(width = nastiXIdBits))
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val size = Reg(UInt(width = nastiXSizeBits))
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val len = Reg(UInt(width = nastiXLenBits))
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val data = Reg(UInt(width = nastiXDataBits))
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val first = Reg(init = Bool(false))
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val is_rtrans = (state === s_read) &&
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(io.hasti.htrans === HTRANS_SEQ ||
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io.hasti.htrans === HTRANS_NONSEQ)
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val rvalid = RegEnable(is_rtrans, Bool(false), io.hasti.hready)
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io.nasti.aw.ready := (state === s_idle)
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io.nasti.ar.ready := (state === s_idle) && !io.nasti.aw.valid
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io.nasti.w.ready := (state === s_write) && io.hasti.hready
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io.nasti.b.valid := (state === s_write_resp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = id)
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io.nasti.r <> r_queue.io.deq
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r_queue.io.enq.valid := io.hasti.hready && rvalid
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r_queue.io.enq.bits := NastiReadDataChannel(
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id = id,
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data = io.hasti.hrdata,
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last = (len === UInt(0)))
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assert(!r_queue.io.enq.valid || r_queue.io.enq.ready,
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"NASTI -> HASTI converter queue overflow")
|
|
|
|
// How many read requests have we not delivered a response for yet?
|
|
val pending_count = r_queue.io.count + rvalid
|
|
|
|
io.hasti.haddr := addr
|
|
io.hasti.hsize := size
|
|
io.hasti.hwrite := (state === s_write)
|
|
io.hasti.hburst := HBURST_INCR
|
|
io.hasti.hprot := UInt(0)
|
|
io.hasti.hwdata := data
|
|
io.hasti.hmastlock := Bool(false)
|
|
io.hasti.htrans := MuxLookup(state, HTRANS_IDLE, Seq(
|
|
s_write -> Mux(io.nasti.w.valid,
|
|
Mux(first, HTRANS_NONSEQ, HTRANS_SEQ),
|
|
Mux(first, HTRANS_IDLE, HTRANS_BUSY)),
|
|
s_read -> MuxCase(HTRANS_BUSY, Seq(
|
|
first -> HTRANS_NONSEQ,
|
|
(pending_count <= UInt(1)) -> HTRANS_SEQ))))
|
|
|
|
when (io.nasti.aw.fire()) {
|
|
first := Bool(true)
|
|
addr := io.nasti.aw.bits.addr
|
|
id := io.nasti.aw.bits.id
|
|
size := io.nasti.aw.bits.size
|
|
state := s_write
|
|
}
|
|
|
|
when (io.nasti.ar.fire()) {
|
|
first := Bool(true)
|
|
addr := io.nasti.ar.bits.addr
|
|
id := io.nasti.ar.bits.id
|
|
size := io.nasti.ar.bits.size
|
|
len := io.nasti.ar.bits.len
|
|
state := s_read
|
|
}
|
|
|
|
when (io.nasti.w.fire()) {
|
|
first := Bool(false)
|
|
addr := addr + (UInt(1) << size)
|
|
data := io.nasti.w.bits.data
|
|
when (io.nasti.w.bits.last) { state := s_write_resp }
|
|
}
|
|
|
|
when (io.nasti.b.fire()) { state := s_idle }
|
|
|
|
when (is_rtrans && io.hasti.hready) {
|
|
first := Bool(false)
|
|
addr := addr + (UInt(1) << size)
|
|
len := len - UInt(1)
|
|
when (len === UInt(0)) { state := s_idle }
|
|
}
|
|
}
|
|
|
|
class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
|
|
val io = new HastiSlaveIO
|
|
|
|
// This is a test SRAM with random delays
|
|
val ready = LFSR16(Bool(true))(0) // Bool(true)
|
|
|
|
// Calculate the bitmask of which bytes are being accessed
|
|
val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize)
|
|
val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) }
|
|
val mask_shift = if (hastiAlignment == 0) UInt(1) else
|
|
mask_wide.asUInt() << io.haddr(hastiAlignment-1,0)
|
|
|
|
// The request had better have been aligned! (AHB-lite requires this)
|
|
if (hastiAlignment >= 1) {
|
|
assert (io.htrans === HTRANS_IDLE || io.htrans === HTRANS_BUSY ||
|
|
(io.haddr & mask_decode.asUInt()(hastiAlignment,1)) === UInt(0),
|
|
"HASTI request not aligned")
|
|
}
|
|
|
|
// The mask and address during the address phase
|
|
val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
|
|
val a_mask = Wire(UInt(width = hastiDataBytes))
|
|
val a_address = io.haddr(depth-1, hastiAlignment)
|
|
val a_write = io.hwrite
|
|
|
|
// for backwards compatibility with chisel2, we needed a static width in definition
|
|
a_mask := mask_shift(hastiDataBytes-1, 0)
|
|
|
|
// The data phase signals
|
|
val d_read = RegEnable(a_request && !a_write, Bool(false), ready)
|
|
val d_mask = RegEnable(a_mask, ready && a_request)
|
|
val d_wdata = Vec.tabulate(hastiDataBytes) { i => io.hwdata(8*(i+1)-1, 8*i) }
|
|
|
|
// AHB writes must occur during the data phase; this poses a structural
|
|
// hazard with reads which must occur during the address phase. To solve
|
|
// this problem, we delay the writes until there is a free cycle.
|
|
//
|
|
// The idea is to record the address information from address phase and
|
|
// then as soon as possible flush the pending write. This cannot be done
|
|
// on a cycle when there is an address phase read, but on any other cycle
|
|
// the write will execute. In the case of reads following a write, the
|
|
// result must bypass data from the pending write into the read if they
|
|
// happen to have matching address.
|
|
|
|
// Remove this once HoldUnless is in chisel3
|
|
def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
|
|
|
|
// Pending write?
|
|
val p_valid = RegInit(Bool(false))
|
|
val p_address = Reg(a_address)
|
|
val p_mask = Reg(a_mask)
|
|
val p_latch_d = RegNext(ready && a_request && a_write, Bool(false))
|
|
val p_wdata = holdUnless(d_wdata, p_latch_d)
|
|
|
|
// Use single-ported memory with byte-write enable
|
|
val mem = SeqMem(1 << (depth-hastiAlignment), Vec(hastiDataBytes, Bits(width = 8)))
|
|
|
|
// Decide is the SRAM port is used for reading or (potentially) writing
|
|
val read = ready && a_request && !a_write
|
|
// In case we are stalled, we need to hold the read data
|
|
val d_rdata = holdUnless(mem.read(a_address, read), RegNext(read))
|
|
// Whenever the port is not needed for reading, execute pending writes
|
|
when (!read && p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) }
|
|
when (!read) { p_valid := Bool(false) }
|
|
|
|
// Record the request for later?
|
|
when (ready && a_request && a_write) {
|
|
p_valid := Bool(true)
|
|
p_address := a_address
|
|
p_mask := a_mask
|
|
}
|
|
|
|
// Does the read need to be muxed with the previous write?
|
|
val a_bypass = a_address === p_address && p_valid
|
|
val d_bypass = RegEnable(a_bypass, ready && a_request)
|
|
|
|
// Mux in data from the pending write
|
|
val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata))
|
|
map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
|
|
// Wipe out any data the master should not see (for testing)
|
|
val outdata = Vec((d_mask.toBools zip muxdata)
|
|
map { case (m, p) => Mux(d_read && ready && m, p, Bits(0)) })
|
|
|
|
// Finally, the outputs
|
|
io.hrdata := outdata.asUInt
|
|
io.hready := ready
|
|
io.hresp := HRESP_OKAY
|
|
}
|
|
|
|
class HastiTest(implicit p: Parameters) extends UnitTest {
|
|
val sram = Module(new HastiTestSRAM(8))
|
|
val bus = Module(new HastiBus(Seq(a => Bool(true))))
|
|
val conv = Module(new HastiMasterIONastiIOConverter)
|
|
val driver = Module(new NastiDriver(32, 8, 2))
|
|
|
|
bus.io.slaves(0) <> sram.io
|
|
bus.io.master <> conv.io.hasti
|
|
conv.io.nasti <> driver.io.nasti
|
|
io.finished := driver.io.finished
|
|
driver.io.start := io.start
|
|
}
|