  Scott JohnsonandGitHub
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f069052969
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Merge pull request #403 from ucb-bar/fix-incisive-warning
Fix Verilog compile warning from Cadence Incisive
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2016-10-18 10:48:32 -07:00 |
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Scott Johnson
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dc4c375c7f
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Silence Verilog compile warning from Cadence Incisive
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2016-10-17 15:44:24 -07:00 |
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Scott Johnson
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96e2cefb34
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Merge branch 'master' into HEAD
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2016-08-22 11:37:30 -07:00 |
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Scott Johnson
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96a868d388
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enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish
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2016-08-19 17:14:54 -07:00 |
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Scott Johnson
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2d12f6689c
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make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
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2016-08-19 16:55:57 -07:00 |
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Scott Johnson
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4dbcc568dc
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reorder code to get rid of messy -1
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2016-08-19 16:55:57 -07:00 |
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Scott Johnson
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f945acf712
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rm race condition on trace_count
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2016-08-19 16:55:57 -07:00 |
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