85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
130b24355f
syncregs: Use synchronizer primitives for IntXing
2017-08-24 17:39:07 -07:00
8b462d1595
syncregs: Use common primitives for AsyncQueue grey code synchronizers
2017-08-24 17:34:07 -07:00
3461cb47cc
syncregs: Make Reset catcher use the synchronizer primitive
2017-08-24 17:26:38 -07:00
c78ee9f0e4
syncreg: Refactor common code
2017-08-24 17:18:04 -07:00
d83a6dc6af
syncregs: Add utilities for Synchronizing Shift Registers
2017-08-24 16:55:17 -07:00
7f683eeb24
async_regs: Make modules have predictable names
2017-08-24 15:33:53 -07:00
0f75ebee92
async_reg: Rename the file to match scalastyle
2017-08-24 15:31:29 -07:00
82df766f4a
Merge pull request #963 from freechipsproject/interrupt-order
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Respect ISA requirements on interrupt priority order
2017-08-18 00:10:19 -07:00
8087a205cc
Remove redundant check in interrupt priority encoding
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chooseInterrupts already sorts M interrupts above S interrupts.
2017-08-17 22:23:42 -07:00
cbe7c51b50
Respect ISA requirements on interrupt priority order
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https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3
2017-08-17 21:27:08 -07:00
b1719cfee0
Fixing requirements for PAddrBits ( #961 )
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Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
2017-08-17 11:53:59 -07:00
1db4b3be9a
Merge pull request #957 from freechipsproject/param_jtag_vpi
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jtag_vpi: Use Parameterized Black Box
2017-08-14 18:37:30 -07:00
8783d51c97
jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed
2017-08-14 17:25:47 -07:00
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
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This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
e945f6e265
Merge pull request #955 from freechipsproject/fix-acquire-before-release
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Fix acquire before release
2017-08-13 18:29:58 -07:00
88332bd885
max-core-cycles: Add a +max-core-cycles PlusArg
2017-08-13 15:47:14 -07:00
3cbc5262ec
Don't permit new acquires until the release queue is drained
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If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492
Actually use the C-channel acquire-before-release queue
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oops...
2017-08-13 13:03:35 -07:00
7387f2a93a
Don't block D-channel when handling a probe
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This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
f191bb994c
PatternPusher: can now expect a certain output ( #952 )
2017-08-11 18:10:27 -07:00
baf769f924
tilelink: add PatternPusher, a device to inject a fixed traffic pattern ( #950 )
2017-08-11 15:07:10 -07:00
a3358f34a0
Fix priority inversion for two back-to-back divides ( #948 )
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If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit. While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
0a591c5b5b
Roll back use of UIntToOH1 ( #946 )
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These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass. This is not yet conclusive.
2017-08-09 18:39:47 -07:00
721770244e
Fix IBuf bug
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Don't examine a packet's xcpt signal if it might be invalid. In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
2017-08-09 09:47:51 -07:00
a9b1410f01
BusBlocker: parameterize page granularity
2017-08-08 17:10:01 -07:00
010ba94474
BusBlocker: rename a variable
2017-08-08 17:00:22 -07:00
6d6fc38787
BusBlocker: lock bit should affect the prior PMP address, not next
2017-08-08 17:00:12 -07:00
809c7e8551
Don't merge stores that manifest WAW hazards
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The following sequence would drop the first store when eccBytes=4:
sb x0, 0(t0)
nop
sb x0, 4(t0)
nop
sb x0, 1(t0)
Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
3ef6e4c9f2
Merge pull request #939 from freechipsproject/bus-blocker
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tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 15:06:55 -07:00
82e13443b2
Merge pull request #937 from freechipsproject/critical-paths
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Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
8f261adc6b
BusBlocker: change default policy to deny
2017-08-08 14:19:59 -07:00
0d76e96b88
tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 13:28:01 -07:00
7935c61c19
Don't report to the DTIM that data is cacheable
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Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
74d309c18e
Make I vs. D a static property of TLB, not an input pin
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The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
e92981b0bd
DRY
2017-08-08 11:46:38 -07:00
62ccba304c
Perform tag error detectoin/correction in same cycle as RAM
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The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
6d1d285464
Merge pull request #933 from freechipsproject/cinst
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Print out the compressed instruction when executing one
2017-08-07 21:40:10 -07:00
cc1e2af336
Merge pull request #934 from freechipsproject/critical-paths
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Revert "Remove one gate from D$ ECC check"
2017-08-07 19:41:08 -07:00
c8f8806df0
Merge pull request #932 from freechipsproject/tl-bus-delayer
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tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 19:01:39 -07:00
c4092dd0cc
tilelink: improve entropy of bus delayer
2017-08-07 17:36:07 -07:00
402907990c
Revert "Remove one gate from D$ ECC check"
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This reverts commit 7d94074b05
2017-08-07 17:33:20 -07:00
2910d6fa2a
tilelink: make bus xbar protected so it can be suggestNamed
2017-08-07 17:30:24 -07:00
fc0d5fcf98
Print out the compressed instruction when executing one
2017-08-07 17:21:53 -07:00
e27072e063
Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse
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Fix ram model source reuse
2017-08-07 16:56:13 -07:00
c457c9cb9f
tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 16:43:06 -07:00
Megan Wachs
Andrew Waterman
Andrew Waterman
Shreesha Srinath
Wesley W. Terpstra
Palmer Dabbelt
Henry Cook