riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,717 Commits 1 Branch 0 Tags
84c2bf550427a64e279438bdbe90ca3604738133
Commit Graph
2 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Shreesha SrinathandWesley W. Terpstra ff1f0170dc changing SystemVerilog params to Verilog style (#801) 
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
 2017-06-16 22:47:12 -07:00
Shreesha SrinathandGitHub 4059d9417f GeneratorUtils: support to elaborate a RawModule 2017-06-15 14:33:02 -07:00