Commit Graph
21 Commits
Author SHA1 Message Date
Schuyler EldridgeandChristopher Celio 933f2ce958 Bump riscv-tools for riscv-fesvr submodule ptr fix (#1275)
The riscv-fesvr submodule was pointing at my local version, oops. This
corrects that in an updated version of riscv-tools.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 14:27:51 -08:00
Schuyler EldridgeandChristopher Celio 8bb397a1b9 Fix VCS argument parsing (#1266)
* Add +permissive/+permissive-off for VCS args

This adds guards around Verilog/VCS options for VCS calls with HTIF's
new `+permissive`/`+permissive-off` options. This enables HTIF to
permissively parse all options inside one of these guards while not
erroring on unknonw commands. This is necessary for VCS, unlike with the
emulator, as HTIF is giving all commands as opposed to only host and
target arguments (like with Verilator/emulator.cc).

* Bump riscv-tools for fesvr VCS fix

* Bump riscv-rools/riscv-fesvr (VCS stderr fix)

Fixes #1266

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-07 22:59:04 -08:00
Schuyler EldridgeandHenry Cook d0b46c5b8f Align RoCCIO with new cloneType (#1270)
- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-06 17:53:51 -08:00
Schuyler EldridgeandHenry Cook 135f06cefc Clarify errors, init jtag error code to zero (#1241)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-16 13:03:51 -08:00
Schuyler Eldridge 355d3b15e8 Merge 'origin/master' into auto-plusargs 2018-01-16 15:45:53 -05:00
Schuyler Eldridge 04af785a5f Emit plusArgs for unit tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 17:54:40 -05:00
Schuyler Eldridge 09c1d034fa Explicitly name PlusArg serializers as *_cHeader
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 17:00:12 -05:00
Schuyler Eldridge cfd49f87c1 Use longname for ElaborationArtefact emission
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 16:55:13 -05:00
Schuyler Eldridge e52d52ae99 Link PlusArg to emulator command line options
- adds a mutable singleton (PlusArgArtefacts) to store information
  about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
  consumed by emulator.cc for correct argument parsing and help text
  generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
  ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
Schuyler EldridgeandMegan Wachs 96dd5d8c38 Emulator example clarifications
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
Schuyler EldridgeandMegan Wachs 7ae6bf7611 Arguments clarification, add examples
This clarifies and provides consistent for the command line arguments
usage text.

This adds a set of examples for running the rocket-chip emulator.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
Schuyler EldridgeandMegan Wachs 1aa87f6578 Make emulator.cc understand HTIF arguments
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
Schuyler EldridgeandMegan Wachs 3ead9a5d2d Move check on VCS inside riscv-fesvr
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
Schuyler EldridgeandAndrew Waterman c61714a465 Pass MODEL variable to emulator.cc
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
2017-03-30 02:08:01 -07:00
Schuyler EldridgeandHenry Cook 7e794212d9 Cleanup emulator.cc, use getopt, add help text (#487)
This changes the emulator to conform to POSIX-style options (e.g.,
short/'-' and long/'--') while preserving legacy option parsing (i.e.,
'+'). Options are read from the user until the first
non-option (either POSIX or legacy) is encountered. This and
everything following is assumed to be the binary and any arguments the
user wants to run on the emulator. All non-options are passed directly
to the DTM. This allows for the same option to be passed, safely, to
both the emulator and the binary, e.g., "+verbose".

This introduces a dependency on <getopt.h>.

Closes #484.
2016-12-13 14:29:57 -08:00
Schuyler EldridgeandHenry Cook 36fe024671 CacheName no longer needed in RoCCInterface
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
Schuyler EldridgeandHenry Cook 624db2034b Make instantiated RoCC use dcacheParams 2016-12-04 19:01:39 -08:00
Schuyler Eldridge e50e4d4c84 build.scala uses space-delimited ROCKETCHIP_ADDONS 2015-12-09 14:17:16 -05:00
Schuyler Eldridge f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE
Fixes #17
2015-09-24 23:56:41 -04:00
Schuyler Eldridge b4cd8c5981 Fix vlsi_mem_gen for Python 2 or 3 2015-06-25 12:48:31 -07:00
Schuyler Eldridge a42832fc70 Fix fpga_mem_gen for Python 2 and 3 Environments
Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
2015-06-25 11:03:33 -07:00