 Richard Xia
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50de991f18
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Fix typo in breakpoint cover property.
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2017-12-04 14:04:24 -08:00 |
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Richard Xia
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4bd9c477ea
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Add cover properties for ECALL exceptions.
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2017-11-30 14:27:04 -08:00 |
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Richard Xia
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29c70501f2
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Add cover properties for exceptions in the core.
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2017-11-30 14:27:04 -08:00 |
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Richard Xia
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f6ec7b765e
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Bump riscv-tools.
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2017-10-31 17:42:05 -07:00 |
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Richard Xia
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5a951799aa
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Add atomics support to DTS JSON file.
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2017-10-18 15:17:53 -07:00 |
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Richard Xia
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167aa7b793
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Bump riscv-tools.
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2017-10-10 14:14:10 -07:00 |
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Richard Xia
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dd5934b6dc
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Bump riscv-tools to bump riscv-tests for mi-csr test fix and pull in stable binutils.
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2017-08-08 16:29:26 -07:00 |
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Richard Xia
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d62787357b
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Rename offchip-interrupts to external-interrupts.
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2017-07-13 15:56:22 -07:00 |
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Richard Xia
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5b46350bc3
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Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
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2017-06-30 17:44:16 -07:00 |
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Richard Xia
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61c39da475
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Check for rvc before declaring illegal instruction after an ebreak.
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2017-06-16 10:49:36 -07:00 |
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Richard Xia
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4e3682f889
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Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
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2016-11-26 12:24:10 -08:00 |
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Richard Xia
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bab504cc3f
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Add various granular and composable configs.
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2016-11-18 11:30:07 -08:00 |
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Richard Xia
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6e5dd45f9a
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Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization fix.
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2016-11-16 11:33:15 -08:00 |
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Richard Xia
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cc5b7d1eb6
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Bump riscv-tools.
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2016-10-26 11:40:49 -07:00 |
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Richard Xia
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183ae58704
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Use a random port number for JTAG VPI.
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2016-10-26 11:40:45 -07:00 |
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Richard Xia
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3fdf40c088
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Change implicit argument to explicit.
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2016-09-16 17:47:31 -07:00 |
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Richard Xia
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63f13ae7ce
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Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
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2016-09-16 17:10:52 -07:00 |
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