riscv/rocket-chip
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467 Commits

Author SHA1 Message Date
Henry Cook
05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Andrew Waterman
78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Andrew Waterman
583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Wesley W. Terpstra
5323cf88dd util: add Option.unzip 2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
dfc815f4d3 rocket: invoke LazyModule at point of use/binding 2017-09-22 14:38:47 -07:00
Henry Cook
81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook
30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0859477d6a127b2f4fde94144190cbc.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook
a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Andrew Waterman
88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman
6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman
9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Andrew Waterman
026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman
5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew Waterman
f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew Waterman
f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman
db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman
aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman
afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman
79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman
ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Henry Cook
57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Henry Cook
8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Andrew Waterman
d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00
Henry Cook
b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook
063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Andrew Waterman
1f606d924f Don't perform in-place correction if there was a recent store (#988) 
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
 2017-09-08 16:26:54 -07:00
Henry Cook
9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook
3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook
e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
e7de7f3e82 Merge pull request #985 from freechipsproject/flop-interrupts 
Add Parameters to diplomatic edges
 2017-09-08 13:16:11 -07:00
Andrew Waterman
53dfc5e9be Remove overzealous assertion (#987) 
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
 2017-09-07 18:17:56 -07:00
Wesley W. Terpstra
1365c5f90c diplomacy: implement DisableMonitors scope 2017-09-07 16:03:35 -07:00
Andrew Waterman
8087a205cc Remove redundant check in interrupt priority encoding 
chooseInterrupts already sorts M interrupts above S interrupts.
 2017-08-17 22:23:42 -07:00
Andrew Waterman
cbe7c51b50 Respect ISA requirements on interrupt priority order 
a62e76cb16
 2017-08-17 21:27:08 -07:00
Andrew Waterman
e945f6e265 Merge pull request #955 from freechipsproject/fix-acquire-before-release 
Fix acquire before release
 2017-08-13 18:29:58 -07:00
Megan Wachs
88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
Andrew Waterman
3cbc5262ec Don't permit new acquires until the release queue is drained 
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
 2017-08-13 13:18:45 -07:00
Andrew Waterman
0190724492 Actually use the C-channel acquire-before-release queue 
oops...
 2017-08-13 13:03:35 -07:00
Andrew Waterman
7387f2a93a Don't block D-channel when handling a probe 
This is an acquire-before-release regression.
 2017-08-12 16:13:24 -07:00
Andrew Waterman
604abd5b07 Only report ECC errors when the RAM was actually read 2017-08-12 15:28:03 -07:00
Andrew Waterman
18fb052fc9 DRY 2017-08-12 15:27:30 -07:00
Andrew Waterman
176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
Andrew Waterman
0a591c5b5b Roll back use of UIntToOH1 (#946) 
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.
 2017-08-09 18:39:47 -07:00
Andrew Waterman
721770244e Fix IBuf bug 
Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
 2017-08-09 09:47:51 -07:00
Andrew Waterman
809c7e8551 Don't merge stores that manifest WAW hazards 
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
 2017-08-08 15:19:05 -07:00