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Commit Graph

7 Commits

Author SHA1 Message Date
Megan Wachs
f68390e458 jtag_vpi: Use a parameter for INIT_DELAY vs constant 2017-09-07 09:06:07 -07:00
Megan Wachs
19eabb6728 jtag_vpi: add some hysterisis for waiting for init_done 2017-09-06 18:13:04 -07:00
Megan Wachs
42ca597478 debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Colin Schmidt
a10d058e1a fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
Yunsup Lee
4a7972be31 connect testharness components via member functions (#236)
to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00