Henry Cook
660355004e
coreplex: TileMasterPortParams inject adapters into SBus
2017-10-10 15:02:50 -07:00
Henry Cook
9026646459
coreplex: first cut at using RocketCrossingParams
2017-10-10 12:02:04 -07:00
Andrew Waterman
36c39d01e4
Factor out most of HasRocketTiles into HasTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
70a4127cb8
Factor out some of HaveRocketTiles into HaveTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00
Henry Cook
8da7aabd51
tile: supply hartid from RocketTileParams
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make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
Henry Cook
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
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This reverts commit 5232a29d7da2dc13669a
2017-10-05 00:26:44 -07:00
Andrew Waterman
32fda51a2c
Get rid of paddrBits from SystemBus ( #1029 )
2017-10-04 12:11:37 -07:00
Henry Cook
cedfb0e784
coreplex: dontTouch the rocket_tile_inputs wire
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which contains hartid.
2017-10-02 19:36:10 -07:00
Wesley W. Terpstra
e07d86aecd
rocket: flip interrupt rendering so cores are on top
2017-09-27 12:46:29 -07:00
Wesley W. Terpstra
0268959c24
rocket: move interrupt synchronizers to correct side of crossing
2017-09-27 12:02:04 -07:00
Wesley W. Terpstra
a27e853101
diplomacy: move rendering properties to edges
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FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
2017-09-26 13:24:36 -07:00
Wesley W. Terpstra
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
Andrew Waterman
afad25fceb
Integrate L1 BusErrorUnit
2017-09-20 00:05:07 -07:00
Henry Cook
b86f4b9bb7
config: use Field defaults over Config defaults
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Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
Henry Cook
9c0bfbd500
tile: remove global Field ResetVectorBits
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Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
2017-09-08 14:50:59 -07:00
Wesley W. Terpstra
1a87ed1193
coreplex: add externalSlaveBuffers configuration option
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910
coreplex: rename externalBuffers to externalMasterBuffers
2017-09-07 16:03:35 -07:00
Henry Cook
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
Megan Wachs
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
Henry Cook
7eeb9dfd88
Merge pull request #899 from freechipsproject/wrapper-dedup
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Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Henry Cook
9a483af6e8
coreplex: naming of tile wrappers
2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965
coreplex: remove superfluous sink and source from wrapper
2017-07-27 14:23:03 -07:00
Yunsup Lee
6916e5cbfb
coreplex: better names for RocketTiles in Verilog ( #890 )
2017-07-25 16:35:31 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
