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Commit Graph

119 Commits

Author SHA1 Message Date
Howard Mao
64ab45e2e4 add RWX permission bits to address map 2015-09-22 09:43:22 -07:00
Howard Mao
27745204eb ErrorSlave returns response of correct length for reads 2015-09-22 09:42:57 -07:00
Howard Mao
4db6124b2a NASTIErrorSlave should print address 2015-09-18 09:42:41 -07:00
Howard Mao
4c3c3c630e add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len 2015-09-10 17:55:10 -07:00
Howard Mao
6387d31c62 add comments and small fixes for NASTI and SMI 2015-09-10 17:33:48 -07:00
Howard Mao
8a8d52da4f add convenient constructors for NASTI channels 2015-09-10 17:33:31 -07:00
Howard Mao
ede1ada053 Add converters and utilities for simpler peripheral interface (SMI) 2015-09-01 14:00:45 -07:00
Howard Mao
75ec7529af implement NASTI Interconnect generating from configuration address map 2015-09-01 14:00:45 -07:00
Howard Mao
b046c57284 make NASTI -> MemIO converter compliant to AXI4 spec 2015-09-01 11:17:38 -07:00
Andrew Waterman
f7d9628de2 Avoid needless use of Vec 2015-08-27 09:40:52 -07:00
Andrew Waterman
3a1dad7994 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:40:24 -07:00
Andrew Waterman
2ff2b43c2c Chisel3 compatibility: use >>Int instead of >>UInt
The latter doesn't contract widths anymore.
2015-08-04 13:13:44 -07:00
Andrew Waterman
e469785f5e bump scala to 2.11.6 2015-08-03 19:51:17 -07:00
Andrew Waterman
d85c46bc60 Chisel3 bulk connect non-commutativity 2015-08-03 19:47:16 -07:00
Andrew Waterman
eb57433f43 Bits -> UInt 2015-07-30 23:57:53 -07:00
Henry Cook
c27945c094 source and build files. source code pulled from uncore and zscale repos 2015-07-29 18:02:58 -07:00
Henry Cook
6a44cd43fd Update README.md 2015-07-28 16:20:18 -07:00
Henry Cook
8eb20cde44 Update LICENSE 2015-07-28 16:07:30 -07:00
Henry Cook
2225a6d5b4 Initial commit 2015-07-28 15:52:07 -07:00