Jack Koenig
64b707cbb6
Bump Chisel and FIRRTL for annotations refactor ( #1261 )
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Also brings in an autoclonetype enhancement and some bug fixes
2018-03-07 10:22:38 -08:00
Henry Cook
8462ea3d5b
coreplex => subsystem
2018-02-21 14:42:24 -08:00
Megan Wachs
c34b940d9a
ElaborationArtefacts: revert unintentional change
2018-02-15 14:23:54 -08:00
Megan Wachs
b95f68447f
RegFieldDesc: Prevent different RegField JSONS from overwriting eachother.
2018-02-15 14:01:47 -08:00
Henry Cook
fe277cf6f0
Merge branch 'master' into auto-plusargs
2018-02-06 18:38:44 -08:00
Henry Cook
7dad486707
util: updates to internal Generator API
2018-01-30 15:19:37 -08:00
Henry Cook
bd50a1a4bc
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
Schuyler Eldridge
cfd49f87c1
Use longname for ElaborationArtefact emission
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 16:55:13 -05:00
Wesley W. Terpstra
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
Yunsup Lee
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Shreesha Srinath
4059d9417f
GeneratorUtils: support to elaborate a RawModule
2017-06-15 14:33:02 -07:00
Wesley W. Terpstra
93b2fa197e
Artefact output ( #545 )
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* build: stop using empty .prm file
* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
e5febcfa33
rocketchip: there are no more useful parameters to dump
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
119ccae9af
rocketchip: don't use explicit cde namespace
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
0a4ef66894
BaseTop: record top module; more general than GraphML
2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
dd9558f45d
rocketchip: generate GraphML output
2016-09-26 14:35:46 -07:00
Henry Cook
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
Henry Cook
47c5d1a992
[WIP] Move RocketTestSuite generation into RocketchipGenerator
2016-09-22 14:31:45 -07:00