Howard Mao
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64ab45e2e4
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add RWX permission bits to address map
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2015-09-22 09:43:22 -07:00 |
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Howard Mao
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27745204eb
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ErrorSlave returns response of correct length for reads
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2015-09-22 09:42:57 -07:00 |
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Howard Mao
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4db6124b2a
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NASTIErrorSlave should print address
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2015-09-18 09:42:41 -07:00 |
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Howard Mao
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4c3c3c630e
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add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len
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2015-09-10 17:55:10 -07:00 |
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Howard Mao
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6387d31c62
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add comments and small fixes for NASTI and SMI
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2015-09-10 17:33:48 -07:00 |
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Howard Mao
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8a8d52da4f
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add convenient constructors for NASTI channels
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2015-09-10 17:33:31 -07:00 |
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Howard Mao
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ede1ada053
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Add converters and utilities for simpler peripheral interface (SMI)
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2015-09-01 14:00:45 -07:00 |
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Howard Mao
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75ec7529af
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implement NASTI Interconnect generating from configuration address map
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2015-09-01 14:00:45 -07:00 |
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Howard Mao
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b046c57284
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make NASTI -> MemIO converter compliant to AXI4 spec
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2015-09-01 11:17:38 -07:00 |
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Andrew Waterman
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f7d9628de2
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Avoid needless use of Vec
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2015-08-27 09:40:52 -07:00 |
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Andrew Waterman
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3a1dad7994
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Use Vec.apply, not Vec.fill, for type nodes
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2015-08-27 09:40:24 -07:00 |
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Andrew Waterman
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2ff2b43c2c
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Chisel3 compatibility: use >>Int instead of >>UInt
The latter doesn't contract widths anymore.
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2015-08-04 13:13:44 -07:00 |
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Andrew Waterman
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e469785f5e
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bump scala to 2.11.6
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2015-08-03 19:51:17 -07:00 |
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Andrew Waterman
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d85c46bc60
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Chisel3 bulk connect non-commutativity
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2015-08-03 19:47:16 -07:00 |
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Andrew Waterman
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eb57433f43
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Bits -> UInt
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2015-07-30 23:57:53 -07:00 |
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Henry Cook
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c27945c094
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source and build files. source code pulled from uncore and zscale repos
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2015-07-29 18:02:58 -07:00 |
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Henry Cook
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6a44cd43fd
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Update README.md
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2015-07-28 16:20:18 -07:00 |
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Henry Cook
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8eb20cde44
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Update LICENSE
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2015-07-28 16:07:30 -07:00 |
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Henry Cook
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2225a6d5b4
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Initial commit
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2015-07-28 15:52:07 -07:00 |
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