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119 Commits

Author SHA1 Message Date
Henry Cook 8462ea3d5b coreplex => subsystem 2018-02-21 14:42:24 -08:00
Andrew Waterman 5e35015651 Minor Rocket fixes to support fLen != xLen 2018-02-20 16:16:39 -08:00
Andrew Waterman ad0b9a0b1b Reduce cases in which FENCE.I must flush D$
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
Jacob Chang 09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… (#1155)
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
2017-12-13 20:16:36 -08:00
Jacob Chang ec3789b365
Add Cross Cover Property Library (#1149)
Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
Andrew Waterman 5c204f98d5
When writing full words to ITIM, ECC errors are correctable (#1148)
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
2017-12-07 16:00:26 -08:00
Gleb Gagarin 7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution 2017-12-01 16:28:28 -08:00
Gleb Gagarin 74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution 2017-12-01 15:50:31 -08:00
Andrew Waterman 890528c641 Avoid data corruption under correctable tag error during flush
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 16:09:44 -08:00
Andrew Waterman 34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)"
This reverts commit 44eb4d12b5.
2017-11-29 16:09:30 -08:00
Andrew Waterman 44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130)
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 09:42:00 -08:00
Andrew Waterman 5155eb6059
Don't emit writeback state machine logic for scratchpad (#1127)
Firrtl can't DCE it because it would require analyzing the state machine.
2017-11-22 18:40:02 -06:00
Wesley W. Terpstra 7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Andrew Waterman 4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman 6176b348dc Invalidate TL error bit in D$ once progress is made 2017-11-07 00:52:18 -08:00
Andrew Waterman f859da85ff Disable covers that don't apply to DTIM 2017-11-03 15:38:13 -07:00
Andrew Waterman d6ede818ee DTIM doesn't accept grants 2017-11-03 15:37:48 -07:00
Henry Cook b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params
Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Henry Cook 1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Andrew Waterman b2bc46471b Conditionalize some covers that are sometimes impossible (#1043) 2017-10-10 17:14:33 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Andrew Waterman f3825270c1 Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Wesley W. Terpstra bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030)
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.

Instead of calling it Overwrite, we decided to split the Acquire type.

If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
Henry Cook 05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry Cook 30c8c8c517 Revert "try to give seqmems clearer names"
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
2017-09-21 18:02:32 -07:00
Henry Cook a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Andrew Waterman 88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman 6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Henry Cook 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems
try to give seqmems clearer names for use with external tools
2017-09-19 17:59:00 -07:00
Henry Cook 8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Andrew Waterman d93d7b9fa4 Only merge stores that aren't yet pending
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
2017-09-17 15:01:07 -07:00
Andrew Waterman 1f606d924f Don't perform in-place correction if there was a recent store (#988)
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
2017-09-08 16:26:54 -07:00
Andrew Waterman 53dfc5e9be Remove overzealous assertion (#987)
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
2017-09-07 18:17:56 -07:00
Andrew Waterman 3cbc5262ec Don't permit new acquires until the release queue is drained
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
Andrew Waterman 0190724492 Actually use the C-channel acquire-before-release queue
oops...
2017-08-13 13:03:35 -07:00
Andrew Waterman 7387f2a93a Don't block D-channel when handling a probe
This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
Andrew Waterman 604abd5b07 Only report ECC errors when the RAM was actually read 2017-08-12 15:28:03 -07:00
Andrew Waterman 18fb052fc9 DRY 2017-08-12 15:27:30 -07:00
Andrew Waterman 176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
Andrew Waterman 809c7e8551 Don't merge stores that manifest WAW hazards
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
Andrew Waterman 82e13443b2 Merge pull request #937 from freechipsproject/critical-paths
Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
Andrew Waterman 7935c61c19 Don't report to the DTIM that data is cacheable
Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
Andrew Waterman 74d309c18e Make I vs. D a static property of TLB, not an input pin
The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
Andrew Waterman e92981b0bd DRY 2017-08-08 11:46:38 -07:00
Andrew Waterman 62ccba304c Perform tag error detectoin/correction in same cycle as RAM
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
Andrew Waterman 402907990c Revert "Remove one gate from D$ ECC check"
This reverts commit 7d94074b05, which
works fine with optimistic behavioral RAMs but not real ones.
2017-08-07 17:33:20 -07:00
Andrew Waterman 7d94074b05 Remove one gate from D$ ECC check
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
Andrew Waterman 83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00