Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Megan Wachs
1e43512142
jtag: Actually apply the sticky bits
2016-09-29 13:49:34 -07:00
Megan Wachs
a4b81aebe0
jtag: Apply sticky bits for error and busy according to the current Debug Spec
2016-09-29 13:49:26 -07:00
Megan Wachs
45bd63fcc6
jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
2016-09-29 13:49:14 -07:00
Colin Schmidt
a10d058e1a
fix warnings in verilog source ( #274 )
2016-09-12 18:25:35 -07:00
Megan Wachs
dd4a50c452
Add JTAG DTM and test support in simulation
...
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
