riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,609 Commits 1 Branch 0 Tags
4059d9417f2d81c89f4e9cbb63506464f25251b5
Commit Graph
8 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Schuyler EldridgeandAndrew Waterman c61714a465 Pass MODEL variable to emulator.cc 
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
 2017-03-30 02:08:01 -07:00
Schuyler EldridgeandHenry Cook 7e794212d9 Cleanup emulator.cc, use getopt, add help text (#487) 
This changes the emulator to conform to POSIX-style options (e.g.,
short/'-' and long/'--') while preserving legacy option parsing (i.e.,
'+'). Options are read from the user until the first
non-option (either POSIX or legacy) is encountered. This and
everything following is assumed to be the binary and any arguments the
user wants to run on the emulator. All non-options are passed directly
to the DTM. This allows for the same option to be passed, safely, to
both the emulator and the binary, e.g., "+verbose".

This introduces a dependency on <getopt.h>.

Closes #484.
 2016-12-13 14:29:57 -08:00
Schuyler EldridgeandHenry Cook 36fe024671 CacheName no longer needed in RoCCInterface 
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
 2016-12-04 19:01:39 -08:00
Schuyler EldridgeandHenry Cook 624db2034b Make instantiated RoCC use dcacheParams 2016-12-04 19:01:39 -08:00
Schuyler Eldridge e50e4d4c84 build.scala uses space-delimited ROCKETCHIP_ADDONS 2015-12-09 14:17:16 -05:00
Schuyler Eldridge f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE 
Fixes #17
 2015-09-24 23:56:41 -04:00
Schuyler Eldridge b4cd8c5981 Fix vlsi_mem_gen for Python 2 or 3 2015-06-25 12:48:31 -07:00
Schuyler Eldridge a42832fc70 Fix fpga_mem_gen for Python 2 and 3 Environments 
Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
 2015-06-25 11:03:33 -07:00