Andrew Waterman
|
e0d849fec5
|
Fix zscale testing
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
|
2015-12-01 17:31:48 -08:00 |
|
Yunsup Lee
|
1e772daeea
|
no spaces in Makefrag
|
2015-11-05 16:42:05 -08:00 |
|
Howard Mao
|
bbf14ddc01
|
use definitions in consts header whenever possible
|
2015-11-05 10:48:32 -08:00 |
|
Yunsup Lee
|
0d245741bc
|
add multichannel NASTI support in Verilog testbench
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
9dabcab9c2
|
Get rid of MemIO in Top and replace with AXI throughout
|
2015-11-05 10:48:32 -08:00 |
|
Yunsup Lee
|
e7802825c3
|
add Zscale testing
|
2015-07-17 12:02:02 -07:00 |
|
Henry Cook
|
d3ccec1044
|
Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
|
2015-07-02 14:43:30 -07:00 |
|
Yunsup Lee
|
70b0f9fd4d
|
error out for PCWM-L, port width mismatch
|
2014-09-25 06:50:50 -07:00 |
|
Yunsup Lee
|
275b72368b
|
add CONFIG to the name of simulator executable
|
2014-09-11 22:11:58 -07:00 |
|
Yunsup Lee
|
02c08a156f
|
generate consts.vh from chisel source
|
2014-09-10 17:14:55 -07:00 |
|
Yunsup Lee
|
ddfd3ce968
|
further generalize fpga/vlsi builds
|
2014-09-08 00:21:57 -07:00 |
|
Yunsup Lee
|
763c57931b
|
fix problem introduced with verilog generation in vsim/fsim
|
2014-09-04 09:49:57 -07:00 |
|
Yunsup Lee
|
c03c09ec31
|
update for rocket-chip release
|
2014-08-31 20:26:55 -07:00 |
|