riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 75f06d6e84 Use generic TileLink width adapter 2016-05-26 16:00:17 -07:00
Andrew Waterman ddfa30e215 Work around zero-width wire limitations 2016-05-26 00:48:54 -07:00
Andrew Waterman 7285f5e6bf Don't drive D$ kill/phys signals for SimpleHellaCacheIF 
They don't do anything.
 2016-04-01 19:31:54 -07:00
Andrew Waterman 13dcb96b7f Update TLB interface 
n.b. no need to set mprv, since prv = S.
 2016-03-14 17:55:19 -07:00