riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,626 Commits 1 Branch 0 Tags
1c97a2a94c6874913f19370d3741cd76e9e4d6d2
Commit Graph
1 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Shreesha SrinathandWesley W. Terpstra ff1f0170dc changing SystemVerilog params to Verilog style (#801) 
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
 2017-06-16 22:47:12 -07:00