Henry Cook
75d4347192
[groundtest] runs tests with new coreplex and top
2016-11-16 17:05:53 -08:00
Henry Cook
408e78e35e
rocketchip Periphery: ExtMem and ExtBus Configs
2016-11-16 16:50:30 -08:00
Henry Cook
2d68f12115
[tl2] give groundtest tile some output nodes
2016-11-14 18:09:40 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Andrew Waterman
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
Howard Mao
50d6738caf
make sure DummyPTW sets all the necessary status and ptbr signals
2016-08-31 22:00:27 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
