riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
379 Commits 1 Branch 0 Tags
09e29e8fe0e4ce1a48a198e9877e10c4b8aacb02
Commit Graph
6 Commits
Author SHA1 Message Date
Yunsup Lee 221007595b allow BACKEND/CONFIG be environment variables 2014-09-17 11:12:08 -07:00
Yunsup Lee 275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee 763c57931b fix problem introduced with verilog generation in vsim/fsim 2014-09-04 09:49:57 -07:00
Scott Beamer 6c6f5a3843 add verilog target to build without simulator 2014-09-03 17:28:45 -07:00
Yunsup Lee c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00