riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,918 Commits 1 Branch 0 Tags 13 MiB
010ba94474
Commit Graph

4918 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5 Several ScratchpadSlavePort bug fixes (#676) 
* only replicate scratch slave d-channel resp when AMO req

* dtim: port can't support put partial mask with holes

* dtim: use \!isRead instead of isAMO

* Fix ScratchpadSlavePort looking at wrong Acquire message

Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
 2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf Unconditionally write badaddr, possibly to zero 
59d33f6b83
 2017-04-12 13:35:02 -07:00
Megan Wachs
bef88c4c30 Add pointers to package dependencies to README (#670) 
Tell people where to look to find package dependency information
 2017-04-11 19:54:46 -07:00
Jim Lawson
907d369bde Remove tests obsoleted by new FP encoding proposal (#672) 2017-04-11 19:12:35 -07:00
Wesley W. Terpstra
37c9ab3459 Merge pull request #671 from ucb-bar/cork-it 
Add a few diplomacy restrictions
 2017-04-11 15:55:37 -07:00
Wesley W. Terpstra
1c36ab8bf7 Fragmenter: forbid multiple sink IDs 
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
 2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822 CacheCork: remove probe support 2017-04-11 12:34:18 -07:00
Andrew Waterman
9a983c12a3 Implement new FP encoding proposal 
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
 2017-04-10 22:38:25 -07:00
Andrew Waterman
470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Wesley W. Terpstra
71bf929505 maskgen: support wider granularity result (#665) 
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
 2017-04-09 20:06:23 -07:00
Andrew Waterman
a43bf2feae Add vectored interrupt support 
4dcaa944ba

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

ba6d88466a
 2017-04-08 00:29:45 -07:00
Megan Wachs
051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. 2017-04-07 16:47:16 -07:00
Megan Wachs
01372e1686 use Wire() correctly to assign a value 2017-04-07 16:47:16 -07:00
Megan Wachs
9ae4838708 jtag: Get rid of chisel deprecation warnings 2017-04-07 16:47:16 -07:00
Megan Wachs
22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. 2017-04-07 16:47:16 -07:00
Megan Wachs
d361e9e343 debug: temporarily leave preexec in place 2017-04-07 16:47:16 -07:00
Megan Wachs
0e2c34b0d6 debug: update register map with new spec 2017-04-07 16:47:16 -07:00
Megan Wachs
df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655) 
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
 2017-04-06 10:33:17 -07:00
Andrew Waterman
5c458322b5 bump chisel for withReset bugfix 2017-04-05 21:46:55 -07:00
Andrew Waterman
c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
Megan Wachs
c5b0b6fb85 debug: bump openOCD version to pick up read_mem fix. Use MemTest64 instead because it's more likely to fail than SimpleS0Test 2017-04-05 15:14:32 -07:00
Megan Wachs
2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
Megan Wachs
b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
Megan Wachs
eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
solomatnikov
127f121ef2 Preserve id_do_fence (#651) 2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Megan Wachs
629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce Debug Controls (#639) 
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
 2017-04-03 13:31:35 -07:00
Yunsup Lee
716533f77f Merge pull request #643 from ucb-bar/update-pmp-encoding 
bump riscv-tools
 2017-03-31 20:52:49 -07:00
Yunsup Lee
983a561720 bump riscv-tools 2017-03-31 19:20:08 -07:00
Andrew Waterman
410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Henry Cook
9f371abf3b Merge pull request #638 from ucb-bar/riscv-tools-on-priv-1.10 
Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v0…
 2017-03-31 01:56:36 -07:00
Henry Cook
e92eaa7156 Merge branch 'master' into riscv-tools-on-priv-1.10 2017-03-30 22:31:29 -07:00
Henry Cook
e8f337e963 Merge pull request #636 from ucb-bar/name-rams 
Name L1$ RAMs consistently
 2017-03-30 22:30:12 -07:00
Megan Wachs
dec567ab0c Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v013 version. 2017-03-30 20:22:54 -07:00
Henry Cook
b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Henry Cook
b6da81a66c Merge pull request #624 from ucb-bar/debug_v013_pr 
Debug v013 [WIP]
 2017-03-30 17:35:26 -07:00
Andrew Waterman
a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Henry Cook
bcaee9834c travis_wait 30 2017-03-30 13:22:33 -07:00
Megan Wachs
0828ebe911 debug_v013: bump fesvr to use autoexec feature for memory writes. 2017-03-30 11:46:28 -07:00
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Schuyler Eldridge
c61714a465 Pass MODEL variable to emulator.cc 
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
 2017-03-30 02:08:01 -07:00