Jacob Chang
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dcda98dcaf
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Disable coverage collection for testbench related verilog files (#1204)
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2018-01-22 16:40:38 -08:00 |
pbing
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a86a9c5564
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Fix omitted parameter (#1014)
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2017-09-25 14:11:28 -07:00 |
Wesley W. Terpstra
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fa867bc478
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plusarg_reader: make synthesis path a no brainer (#947)
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2017-08-10 16:35:30 -07:00 |
Shreesha Srinath
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ff1f0170dc
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changing SystemVerilog params to Verilog style (#801)
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
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2017-06-16 22:47:12 -07:00 |
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Wesley W. Terpstra
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6a7e6ab325
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plusarg_reader: support verilator
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2017-06-01 10:59:45 -07:00 |
Andrew Waterman
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618468a06b
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Make plusarg_reader default args work with VCS (#765)
Resolves #764
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2017-05-24 21:38:56 -07:00 |
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Wesley W. Terpstra
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7f1d3c445f
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Plusargs -- tilelink timeout detection from the command line (#752)
* util: PlusArg gives Chisel access to the command-line
* tilelink2: add a progress watchdog to Monitors
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2017-05-18 22:49:59 -07:00 |