1
0
Fork 0
Commit Graph

114 Commits

Author SHA1 Message Date
Schuyler Eldridge d0b46c5b8f Align RoCCIO with new cloneType (#1270)
- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-06 17:53:51 -08:00
Henry Cook 8462ea3d5b coreplex => subsystem 2018-02-21 14:42:24 -08:00
Andrew Waterman b487448961 Add FPUParams.fLen option, decoupled from xLen 2018-02-20 16:16:39 -08:00
Andrew Waterman 5e35015651 Minor Rocket fixes to support fLen != xLen 2018-02-20 16:16:39 -08:00
Andrew Waterman 1bac2cbdf8 Give Rocket priority over DTIM TL port
The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline.  Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads.  Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
Andrew Waterman 9f6d586e8c
Add PLIC covers (#1229)
* Add another FPU hazard cover

* Add some PLIC covers
2018-02-06 17:33:33 -08:00
Andrew Waterman 7a0252fdfc Add some covers for FPU structural hazards 2018-01-23 16:32:03 -08:00
Henry Cook 15c54b1c5a tile: intSinkNode belongs in HasExternalInterrupts 2018-01-08 19:38:10 -08:00
Henry Cook 11e5b620f8 tile: disable more monitors on slave port 2018-01-08 18:42:25 -08:00
Henry Cook 320900f76c tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
Henry Cook b0e1bc3071 tile: cake reduction
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
Henry Cook efe7165b54 tile: BaseTile refactor, pt 2
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
Henry Cook 1579ddb97e tile: removed RocketTileWrapper. RocketTile now HasCrossing. 2017-12-28 14:00:13 -08:00
Henry Cook 1cd018546c tile: BaseTile refactor, pt 1
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
Henry Cook ddaeedf2d0 coreplex: make HasTiles more generic
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
2017-12-20 17:18:55 -08:00
Wesley W. Terpstra 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
2017-11-20 18:09:57 -08:00
Wesley W. Terpstra baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS 2017-11-20 17:42:06 -08:00
Henry Cook b625e68360
tile: put a BasicBusBlocker inside RocketTile (#1115)
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
2017-11-17 17:26:48 -08:00
Andrew Waterman 4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman efdb418559
Merge pull request #1098 from freechipsproject/frontend
Frontend improvements
2017-11-09 17:44:38 -08:00
Andrew Waterman d0c6cbba6b Improve frontend branch prediction
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
2017-11-09 00:00:56 -08:00
Andrew Waterman be3a3e0187 Generate local interrupt #128 on bus errors
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
2017-11-06 18:03:59 -08:00
Wesley W. Terpstra 7cf5d4aa90 diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
Wesley W. Terpstra 9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra e30906589f coreplex: refactor crossings to use node pattern 2017-10-26 13:04:32 -07:00
Henry Cook b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Megan Wachs e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054)
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
2017-10-13 15:20:35 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Wesley W. Terpstra d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) 2017-10-09 21:03:18 -07:00
Andrew Waterman 2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
2017-10-09 16:48:04 -07:00
Andrew Waterman 986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits
This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
Andrew Waterman 70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Henry Styles 5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Henry Cook 8da7aabd51 tile: supply hartid from RocketTileParams
make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
Andrew Waterman 7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend
It is more generally useful.
2017-10-03 17:34:18 -07:00
Andrew Waterman 5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman 09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman ab0821f25b Move microarchitecture-neutral params from Rocket to Core
This makes some of the units more reusable.
2017-10-03 17:34:18 -07:00
Wesley W. Terpstra 0268959c24 rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:02:04 -07:00
Wesley W. Terpstra a27e853101 diplomacy: move rendering properties to edges
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
2017-09-26 13:24:36 -07:00
Wesley W. Terpstra 60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra 9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra d89ee9d9d4 nodes: grab a name on construction 2017-09-22 14:38:47 -07:00
Henry Cook e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00