488 lines
18 KiB
Scala
488 lines
18 KiB
Scala
package rocket
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import Chisel._
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import Constants._
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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}
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class TrackerAllocReq extends Bundle {
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val xact_init = new TransactionInit()
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val init_tile_id = Bits(width = TILE_ID_BITS)
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val data_valid = Bool()
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}
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionInit extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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class TransactionInitData extends MemData
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class TransactionAbort extends Bundle {
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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}
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class ProbeRequest extends Bundle {
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val p_type = Bits(width = PTYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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class ProbeReply extends Bundle {
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val p_type = Bits(width = PTYPE_BITS)
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val has_data = Bool()
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends MemData
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class TransactionReply extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class TransactionReplyData extends MemData
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class TransactionFinish extends Bundle {
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ioTileLink extends Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
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val xact_init_data = (new ioDecoupled) { new TransactionInitData() }.flip
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_rep_data = (new ioDecoupled) { new TransactionReplyData() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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}
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trait CoherencePolicy {
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def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
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val store = (cmd === M_XWR)
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val load = (cmd === M_XRD)
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val amo = cmd(3).toBool
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val read = load || amo || (cmd === M_PFR)
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val write = store || amo || (cmd === M_PFW)
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(read, write)
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}
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}
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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( state === tileClean || state === tileDirty)
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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def newState(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid)
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, state)
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}
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}
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trait FourStateCoherence extends CoherencePolicy {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
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(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileExclusiveDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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// TODO: New funcs as compared to incoherent protocol:
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def newState(cmd: Bits, state: UFix): UFix
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def newStateOnHit(cmd: Bits, state: UFix): UFix
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def newStateOnPrimaryMiss(cmd: Bits): UFix
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
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def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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val state = UFix(0)
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switch(incoming.p_type) {
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is(probeInvalidate) { state := tileInvalid }
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is(probeDowngrade) { state := tileShared }
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}
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state.toBits
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}
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}
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class XactTracker(id: Int) extends Component with CoherencePolicy {
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val io = new Bundle {
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_x_init = Bool(OUTPUT)
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val pop_x_init_data = Bool(OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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val s_idle :: s_mem_r :: s_mem_w :: mem_wr :: s_probe :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val addr_ = Reg{ Bits() }
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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val mem_count = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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io.addr := addr_
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io.init_tile_id := init_tile_id_
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io.tile_xact_id := tile_xact_id_
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io.sharer_count := UFix(NTILES) // TODO: Broadcast only
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io.t_type := t_type_
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/*
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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}
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class TrackerAllocReq extends Bundle {
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val xact_init = new TransactionInit()
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val init_tile_id = Bits(width = TILE_ID_BITS)
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val data_valid = Bool()
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*/
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/*
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when( alloc_req.valid && can_alloc ) {
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valid := Bool(true)
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addr := alloc_req.bits.xact_init.address
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t_type := alloc_req.bits.xact_init.t_type
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init_tile_id := alloc_req.bits.init_tile_id
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tile_xact_id := alloc_req.bits.xact_init.tile_xact_id
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[counter] := REFILL_CYCLES-1 if alloc_req.bits.xact_init.has_data else 0
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}
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when ( alloc_req.bits.data_valid ) {
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io.mem_req.valid :=
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io.mem_req.bits.rw :=
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io.mem_req.bits.addr :=
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io.mem_req.bits.tag :=
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io.mem_req.bits.data_idx :=
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io.mem_req.bits.is_probe_rep :=
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:= io.mem.ready
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}
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when( p_rep_has_data ) {
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io.mem_req.valid :=
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io.mem_req.bits.rw :=
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io.mem_req.bits.addr :=
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io.mem_req.bits.tag :=
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io.mem_req.bits.data_idx :=
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io.mem_req.bits.is_probe_rep :=
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:= io.mem.ready
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}
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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push_p_req = Bits(0, width = NTILES)
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pop_p_rep = Bits(0, width = NTILES)
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pop_p_rep_data = Bits(0, width = NTILES)
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pop_x_init = Bool(false)
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pop_x_init_data = Bool(false)
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send_x_rep_ack = Bool(false)
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}
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*/
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//TODO: Decrement the probe count when final data piece is written
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// Connent io.mem.ready sig to correct pop* outputs
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// P_rep and x_init must be popped on same cycle of receipt
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}
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abstract class CoherenceHub extends Component with CoherencePolicy
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class CoherenceHubNull extends Component {
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val io = new Bundle {
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val tile = new ioTileLink()
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val mem = new ioMem()
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}
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val x_init = io.tile.xact_init
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val is_write = x_init.bits.t_type === X_WRITE_UNCACHED
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x_init.ready := io.mem.req_rdy
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io.mem.req_val := x_init.valid
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io.mem.req_rw := is_write
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io.mem.req_tag := x_init.bits.tile_xact_id
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io.mem.req_addr := x_init.bits.address
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val x_rep = io.tile.xact_rep
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x_rep.bits.t_type := Bits(width = TTYPE_BITS)
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x_rep.bits.has_data := !is_write
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x_rep.bits.tile_xact_id := Mux(is_write, x_init.bits.tile_xact_id, io.mem.resp_tag)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.valid := io.mem.resp_val
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//TODO:
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val x_init_data = io.tile.xact_init_data
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val x_rep_data = io.tile.xact_rep_data
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x_init_data.ready := io.mem.req_rdy
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io.mem.req_wdata := x_init_data.bits.data
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x_rep_data.bits.data := io.mem.resp_data
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x_rep_data.valid := io.mem.resp_val
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// Should be:
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//io.mem.req_data <> x_init_data
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//x_rep_data <> io.mem.resp_data
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}
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class CoherenceHubNoDir extends CoherenceHub {
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
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addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
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}
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def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
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val ret = Wire() { Bits(width = TTYPE_BITS) }
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switch (t_type) {
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is(X_READ_SHARED) { ret := Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE) }
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is(X_READ_EXCLUSIVE) { ret := X_READ_EXCLUSIVE }
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is(X_READ_UNCACHED) { ret := X_READ_UNCACHED }
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is(X_WRITE_UNCACHED) { ret := X_WRITE_UNCACHED }
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}
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ret
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}
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioMem
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_data_idx_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val p_rep_cnt_dec_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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val p_req_cnt_inc_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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for( i <- 0 until NGLOBAL_XACTS) {
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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init_tile_id_arr.write( UFix(i), trackerList(i).io.init_tile_id)
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tile_xact_id_arr.write( UFix(i), trackerList(i).io.tile_xact_id)
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t_type_arr.write( UFix(i), trackerList(i).io.t_type)
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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send_x_rep_ack_arr.write(UFix(i), trackerList(i).io.send_x_rep_ack)
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trackerList(i).io.xact_finish := do_free_arr.read(UFix(i))
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trackerList(i).io.p_rep_has_data := p_rep_has_data_arr.read(UFix(i))
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trackerList(i).io.p_rep_data_idx := p_rep_data_idx_arr.read(UFix(i))
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trackerList(i).io.p_rep_cnt_dec := p_rep_cnt_dec_arr.read(UFix(i))
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trackerList(i).io.p_req_cnt_inc := p_req_cnt_inc_arr.read(UFix(i))
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}
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// Free finished transactions
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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do_free_arr.write(finish.bits.global_xact_id, finish.valid)
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finish.ready := Bool(true)
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}
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// Reply to initial requestor
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// Forward memory responses from mem to tile
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val xrep_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val xrep_cnt_next = xrep_cnt + UFix(1)
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when (io.mem.resp_val) { xrep_cnt := xrep_cnt_next }
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val idx = io.mem.resp_tag
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val readys = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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io.tiles(j).xact_rep.bits.t_type := getTransactionReplyType(t_type_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tile_xact_id := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.global_xact_id := idx
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io.tiles(j).xact_rep_data.bits.data := io.mem.resp_data
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readys := Mux(xrep_cnt === UFix(0), io.tiles(j).xact_rep.ready && io.tiles(j).xact_rep_data.ready, io.tiles(j).xact_rep_data.ready)
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io.tiles(j).xact_rep.valid := (UFix(j) === init_tile_id_arr.read(idx)) && ((io.mem.resp_val && xrep_cnt === UFix(0)) || send_x_rep_ack_arr.read(idx))
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io.tiles(j).xact_rep_data.valid := (UFix(j) === init_tile_id_arr.read(idx))
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}
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// If there were a ready signal due to e.g. intervening network use:
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//io.mem.resp_rdy := readys(init_tile_id_arr.read(idx)).xact_rep.ready
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// Create an arbiter for the one memory port
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// We have to arbitrate between the different trackers' memory requests
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// and once we have picked a request, get the right write data
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val mem_req_arb = (new Arbiter(NGLOBAL_XACTS)) { new HubMemReq() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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mem_req_arb.io.in(i) <> trackerList(i).io.mem_req
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}
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mem_req_arb.io.out.ready := io.mem.req_rdy
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io.mem.req_val := mem_req_arb.io.out.valid
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io.mem.req_rw := mem_req_arb.io.out.bits.rw
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io.mem.req_tag := mem_req_arb.io.out.bits.tag
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io.mem.req_addr := mem_req_arb.io.out.bits.addr
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io.mem.req_wdata := MuxLookup(mem_req_arb.io.out.bits.data_idx,
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Bits(0, width = MEM_DATA_BITS),
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(0 until NTILES).map( j =>
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UFix(j) -> Mux(mem_req_arb.io.out.bits.is_probe_rep,
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io.tiles(j).probe_rep_data.bits.data,
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io.tiles(j).xact_init_data.bits.data)))
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// Handle probe replies, which may or may not have data
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for( j <- 0 until NTILES ) {
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val p_rep = io.tiles(j).probe_rep
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val p_rep_data = io.tiles(j).probe_rep_data
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val idx = p_rep.bits.global_xact_id
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p_rep_has_data_arr.write(idx, p_rep.valid && p_rep.bits.has_data && p_rep_data.valid)
|
|
p_rep_data_idx_arr.write(idx, UFix(j))
|
|
p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _)
|
|
p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
|
|
}
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
val flags = Bits(width = NTILES)
|
|
for( j <- 0 until NTILES) {
|
|
val p_rep = io.tiles(j).probe_rep
|
|
flags(j) := p_rep.valid && !p_rep.bits.has_data && (p_rep.bits.global_xact_id === UFix(i))
|
|
}
|
|
p_rep_cnt_dec_arr.write(UFix(i), flags)
|
|
}
|
|
|
|
// Nack conflicting transaction init attempts
|
|
val aborting = Wire() { Bits(width = NTILES) }
|
|
for( j <- 0 until NTILES ) {
|
|
val x_init = io.tiles(j).xact_init
|
|
val x_abort = io.tiles(j).xact_abort
|
|
val conflicts = Bits(width = NGLOBAL_XACTS)
|
|
for( i <- 0 until NGLOBAL_XACTS) {
|
|
val t = trackerList(i).io
|
|
conflicts(i) := t.busy(i) && coherenceConflict(t.addr, x_init.bits.address) &&
|
|
!(x_init.bits.has_data && (UFix(j) === t.init_tile_id))
|
|
// Don't abort writebacks stalled on mem.
|
|
// TODO: This assumes overlapped writeback init reqs to
|
|
// the same addr will never be issued; is this ok?
|
|
}
|
|
x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
|
|
val want_to_abort = conflicts.orR || busy_arr.toBits.andR
|
|
x_abort.valid := want_to_abort && x_init.valid
|
|
aborting(j) := want_to_abort && x_abort.ready
|
|
}
|
|
|
|
// Handle transaction initiation requests
|
|
// Only one allocation per cycle
|
|
// Init requests may or may not have data
|
|
val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
|
|
val init_arb = (new Arbiter(NTILES)) { new TrackerAllocReq() }
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
alloc_arb.io.in(i).valid := !trackerList(i).io.busy
|
|
trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready
|
|
trackerList(i).io.alloc_req.bits := init_arb.io.out.bits
|
|
trackerList(i).io.alloc_req.valid := init_arb.io.out.valid
|
|
}
|
|
|
|
for( j <- 0 until NTILES ) {
|
|
val x_init = io.tiles(j).xact_init
|
|
val x_init_data = io.tiles(j).xact_init_data
|
|
init_arb.io.in(j).valid := x_init.valid
|
|
init_arb.io.in(j).bits.xact_init := x_init.bits
|
|
init_arb.io.in(j).bits.init_tile_id := UFix(j)
|
|
init_arb.io.in(j).bits.data_valid := x_init_data.valid
|
|
x_init.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init && init_arb.io.out.bits.init_tile_id === UFix(j)))(_||_)
|
|
x_init_data.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init_data && init_arb.io.out.bits.init_tile_id === UFix(j)))(_||_)
|
|
}
|
|
|
|
alloc_arb.io.out.ready := init_arb.io.out.valid && !busy_arr.toBits.andR &&
|
|
!foldR(trackerList.map(t => t.io.busy && coherenceConflict(t.io.addr, init_arb.io.out.bits.xact_init.address)))(_||_)
|
|
|
|
|
|
// Handle probe request generation
|
|
// Must arbitrate for each request port
|
|
val p_req_arb_arr = List.fill(NTILES)((new Arbiter(NGLOBAL_XACTS)) { new ProbeRequest() })
|
|
for( j <- 0 until NTILES ) {
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
val t = trackerList(i).io
|
|
p_req_arb_arr(j).io.in(i).bits := t.probe_req.bits
|
|
p_req_arb_arr(j).io.in(i).valid := t.probe_req.valid && t.push_p_req(j)
|
|
}
|
|
p_req_arb_arr(j).io.out <> io.tiles(j).probe_req
|
|
}
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
val flags = Bits(width = NTILES)
|
|
for( j <- 0 until NTILES ) {
|
|
flags(j) := p_req_arb_arr(j).io.in(i).ready
|
|
}
|
|
p_rep_cnt_dec_arr.write(UFix(i), flags)
|
|
}
|
|
|
|
}
|