finished xact_rep transactor in coherence hub
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c3646e2e64
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@ -2,6 +2,7 @@ package Top {
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import Chisel._
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import Constants._
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import hwacha.GenArray
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class TransactionInit extends Bundle {
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val ttype = Bits(width = TTYPE_BITS)
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@ -146,10 +147,12 @@ class XactTracker(id: Int) extends Component {
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val xact_rep = (new ioDecoupled) { new TransactionReply() }.flip
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val mem_req = (new ioDecoupled) { new MemReq() }.flip
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val xact_finish = Bool(INPUT)
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val tile_id_in = Bits(TILE_ID_BITS, INPUT)
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val tile_id_out = Bits(TILE_ID_BITS, OUTPUT)
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val ongoing_addr = Bits(PADDR_BITS, OUTPUT)
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val ttype = Bits(TTYPE_BITS, OUTPUT)
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}
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val valid = Reg(resetVal = Bool(false))
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@ -164,47 +167,104 @@ class XactTracker(id: Int) extends Component {
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abstract class CoherenceHub extends Component
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class CoherenceHubNoDir extends CoherenceHub {
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
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addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
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}
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def getTransactionReplyType(ttype: UFix, count: UFix): Bits = {
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val ret = Wire() { Bits(width = TTYPE_BITS) }
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switch (ttype) {
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is(X_READ_SHARED) { ret := Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE) }
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is(X_READ_EXCLUSIVE) { ret := X_READ_EXCLUSIVE }
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is(X_READ_UNCACHED) { ret := X_READ_UNCACHED }
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is(X_WRITE_UNCACHED) { ret := X_WRITE_UNCACHED }
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}
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ret
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}
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioDCache().flip
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val busy_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val ttype_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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for( i <- 0 until NGLOBAL_XACTS) {
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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tile_id_arr.write( UFix(i), trackerList(i).io.tile_id)
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tile_xact_id_arr.write(UFix(i), trackerList(i).io.tile_xact_id)
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ttype_arr.write( UFix(i), trackerList(i).io.ttype)
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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trackerList(i).io.xact_finish := free_arr.read(UFix(i))
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}
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// In parallel, every cycle: nack conflicting transactions, free finished ones
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for( j <- 0 until NTILES ) {
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val init = io.tiles(j).xact_init
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val abort = io.tiles(j).xact_abort
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val conflicts = Bits(width = NGLOBAL_XACTS)
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val busys = Bits(width = NGLOBAL_XACTS)
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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busys(i) := t.busy
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conflicts(i) := t.busy && init.valid && (t.ongoing_addr === init.bits.address)
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conflicts(i) := t.busy(i) && coherenceConflict(t.addr, init.bits.address)
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}
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abort.valid := conflicts.orR || busys.andR
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abort.valid := init.valid && (conflicts.orR || busy_arr.flatten().andR)
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abort.bits.tileTransactionID := init.bits.tileTransactionID
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//if abort.rdy, init.pop()
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// TODO:
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// Reg(aborted) := (abort.ready && abort.valid)
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// Reg(allocated) : = had_priority(j) & !(abort.ready && abort.valid)
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// init.rdy = aborted || allocated
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}
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/*
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// Todo: which implementation is clearer?
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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val freed = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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freed(j) := finish.valid && (UFix(i) === finish.bits.globalTransactionID)
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free(j) := finish.valid && (UFix(i) === finish.bits.globalTransactionID)
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finish.ready := Bool(true) // finsh.pop()
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}
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t.xact_finish := freed.orR
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//finish.pop()
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}
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*/
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free_arr := Bits(0, width=NGLOBAL_XACTS)
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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when(finish.valid) {
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free_arr.write(finish.bits.globalTransactionID, Bool(true))
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}
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finish.ready := Bool(true)
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}
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// Forward memory responses from mem to tile
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//for( j <- until NTILES ) {
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// tiles(j).xact_rep.ttype =
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// tiles(j).xact_rep.tileTransactionID =
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// tiles(j).xact_rep.globalTransactionID =
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// val data = Bits
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//
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val xrep_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val xrep_cnt_next = xrep_cnt + UFix(1)
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when (io.mem.resp_val) { xrep_cnt := xrep_cnt_next }
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val idx = io.mem.resp_tag
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val readys = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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io.tiles(j).xact_rep.bits.ttype := getTransactionReplyType(ttype_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tileTransactionID := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.globalTransactionID := idx
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io.tiles(j).xact_rep_data.bits.data := io.mem.resp_data
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readys := Mux(xrep_cnt === UFix(0), io.tiles(j).xact_rep.ready && io.tiles(j).xact_rep_data.ready, io.tiles(j).xact_rep_data.ready)
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val this_rep_valid = UFix(j) === tile_id_arr.read(idx) && io.mem.resp_val
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io.tiles(j).xact_rep.valid := this_rep_valid && xrep_cnt === UFix(0)
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io.tiles(j).xact_rep_data.valid := this_rep_valid
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}
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// If there were a ready signal due to e.g. intervening network:
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//io.mem.resp_rdy := readys(tile_id_arr.read(idx)).xact_rep.ready
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// Pick a single request of these types to process
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//val xact_init_arb = (new Arbiter(NTILES)) { new TransactionInit() }
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//val probe_reply_arb = (new Arbiter(NTILES)) { new ProbeReply() }
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