Improved TileIO organization, beginnings of hub implementation
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33a26424bd
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c3646e2e64
@ -24,6 +24,9 @@ class ProbeReply extends Bundle {
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val ptype = Bits(width = PTYPE_BITS)
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val hasData = Bool()
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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@ -31,6 +34,9 @@ class TransactionReply extends Bundle {
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val ttype = Bits(width = TTYPE_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class TransactionReplyData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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@ -39,12 +45,14 @@ class TransactionFinish extends Bundle {
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}
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class ioTileLink extends Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_rep_data = (new ioDecoupled) { new TransactionReplyData() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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}
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trait CoherencePolicy {
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@ -130,6 +138,78 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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}
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class XactTracker(id: Int) extends Component {
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val io = new Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }.flip
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val mem_req = (new ioDecoupled) { new MemReq() }.flip
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val xact_finish = Bool(INPUT)
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val tile_id_in = Bits(TILE_ID_BITS, INPUT)
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val tile_id_out = Bits(TILE_ID_BITS, OUTPUT)
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val ongoing_addr = Bits(PADDR_BITS, OUTPUT)
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val busy = Bool(OUTPUT)
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}
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val valid = Reg(resetVal = Bool(false))
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val addr = Reg{ Bits() }
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val ttype = Reg{ Bits() }
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val tile_id = Reg{ Bits() }
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val tile_xact_id = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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}
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abstract class CoherenceHub extends Component
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class CoherenceHubNoDir extends CoherenceHub {
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioDCache().flip
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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// In parallel, every cycle: nack conflicting transactions, free finished ones
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for( j <- 0 until NTILES ) {
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val init = io.tiles(j).xact_init
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val abort = io.tiles(j).xact_abort
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val conflicts = Bits(width = NGLOBAL_XACTS)
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val busys = Bits(width = NGLOBAL_XACTS)
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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busys(i) := t.busy
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conflicts(i) := t.busy && init.valid && (t.ongoing_addr === init.bits.address)
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}
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abort.valid := conflicts.orR || busys.andR
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abort.bits.tileTransactionID := init.bits.tileTransactionID
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//if abort.rdy, init.pop()
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}
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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val freed = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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freed(j) := finish.valid && (UFix(i) === finish.bits.globalTransactionID)
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}
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t.xact_finish := freed.orR
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//finish.pop()
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}
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// Forward memory responses from mem to tile
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//for( j <- until NTILES ) {
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// tiles(j).xact_rep.ttype =
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// tiles(j).xact_rep.tileTransactionID =
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// tiles(j).xact_rep.globalTransactionID =
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// val data = Bits
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//
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// Pick a single request of these types to process
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//val xact_init_arb = (new Arbiter(NTILES)) { new TransactionInit() }
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//val probe_reply_arb = (new Arbiter(NTILES)) { new ProbeReply() }
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}
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}
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