diff --git a/coreplex/src/main/scala/Configs.scala b/coreplex/src/main/scala/Configs.scala index 894cdeb8..67a9e5c7 100644 --- a/coreplex/src/main/scala/Configs.scala +++ b/coreplex/src/main/scala/Configs.scala @@ -32,12 +32,7 @@ class BaseCoreplexConfig extends Config ( pname match { //Memory Parameters case PAddrBits => 32 - case PgIdxBits => 12 case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ - case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8) - case VPNBits => site(PgLevels) * site(PgLevelBits) - case PPNBits => site(PAddrBits) - site(PgIdxBits) - case VAddrBits => site(VPNBits) + site(PgIdxBits) case ASIdBits => 7 //Params used by all caches case NSets => findBy(CacheName) @@ -64,16 +59,15 @@ class BaseCoreplexConfig extends Config ( }:PF case ECCCode => None case Replacer => () => new RandomReplacement(site(NWays)) - case AmoAluOperandBits => site(XLen) //L1InstCache case BtbKey => BtbParameters() //L1DataCache - case WordBits => site(XLen) case StoreDataQueueDepth => 17 case ReplayQueueDepth => 16 case NMSHRs => Knob("L1D_MSHRS") case LRSCCycles => 32 //L2 Memory System Params + case AmoAluOperandBits => site(XLen) case NAcquireTransactors => 7 case L2StoreDataQueueDepth => 1 case L2DirectoryRepresentation => new NullRepresentation(site(NTiles)) @@ -102,13 +96,13 @@ class BaseCoreplexConfig extends Config ( case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _) case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _) //Rocket Core Constants + case CoreInstBits => if (site(UseCompressed)) 16 else 32 case FetchWidth => if (site(UseCompressed)) 2 else 1 case RetireWidth => 1 case UseVM => true case UseUser => true case UseDebug => true case NBreakpoints => 1 - case UsePerfCounters => true case FastLoadWord => true case FastLoadByte => false case MulUnroll => 8 @@ -141,8 +135,6 @@ class BaseCoreplexConfig extends Config ( case FDivSqrt => true case SFMALatency => 2 case DFMALatency => 3 - case CoreInstBits => if (site(UseCompressed)) 16 else 32 - case CoreDataBits => site(XLen) case NCustomMRWCSRs => 0 case ResetVector => BigInt(0x1000) case MtvecInit => BigInt(0x1010) diff --git a/groundtest/src/main/scala/TraceGen.scala b/groundtest/src/main/scala/TraceGen.scala index 5070f48f..249ee99c 100644 --- a/groundtest/src/main/scala/TraceGen.scala +++ b/groundtest/src/main/scala/TraceGen.scala @@ -63,7 +63,7 @@ trait HasTraceGenParams { val numBitsInId = log2Up(numGens) val numReqsPerGen = p(GeneratorKey).maxRequests val memRespTimeout = 8192 - val numBitsInWord = p(WordBits) + val numBitsInWord = p(XLen) val numBytesInWord = numBitsInWord / 8 val numBitsInWordOffset = log2Up(numBytesInWord) val addressBag = p(AddressBag) diff --git a/junctions/src/main/scala/addrmap.scala b/junctions/src/main/scala/addrmap.scala index e796f8df..095c2da9 100644 --- a/junctions/src/main/scala/addrmap.scala +++ b/junctions/src/main/scala/addrmap.scala @@ -7,28 +7,12 @@ import cde.{Parameters, Field} import scala.collection.mutable.HashMap case object PAddrBits extends Field[Int] -case object VAddrBits extends Field[Int] -case object PgIdxBits extends Field[Int] -case object PgLevels extends Field[Int] -case object PgLevelBits extends Field[Int] -case object ASIdBits extends Field[Int] -case object PPNBits extends Field[Int] -case object VPNBits extends Field[Int] - case object GlobalAddrMap extends Field[AddrMap] trait HasAddrMapParameters { implicit val p: Parameters val paddrBits = p(PAddrBits) - val vaddrBits = p(VAddrBits) - val pgIdxBits = p(PgIdxBits) - val ppnBits = p(PPNBits) - val vpnBits = p(VPNBits) - val pgLevels = p(PgLevels) - val pgLevelBits = p(PgLevelBits) - val asIdBits = p(ASIdBits) - val addrMap = p(GlobalAddrMap) } diff --git a/riscv-tools b/riscv-tools index d34419ff..745e74af 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit d34419ff39072d999371641da520cdce687fd21c +Subproject commit 745e74afb56ecba090669615d4ac9c9b9b96c653 diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index 2b93381a..e2edb148 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -404,7 +404,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { // AMOs if (usingAtomics) { - val amoalu = Module(new AMOALU) + val amoalu = Module(new AMOALU(xLen)) amoalu.io.addr := pstore1_addr amoalu.io.cmd := pstore1_cmd amoalu.io.typ := pstore1_typ diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index f310bd55..b8227dcb 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -12,14 +12,13 @@ import uncore.constants._ import cde.{Parameters, Field} import Util._ -case object WordBits extends Field[Int] case object StoreDataQueueDepth extends Field[Int] case object ReplayQueueDepth extends Field[Int] case object NMSHRs extends Field[Int] case object LRSCCycles extends Field[Int] trait HasL1HellaCacheParameters extends HasL1CacheParameters { - val wordBits = p(WordBits) + val wordBits = xLen // really, xLen max fLen val wordBytes = wordBits/8 val wordOffBits = log2Up(wordBytes) val beatBytes = p(CacheBlockBytes) / outerDataBeats @@ -953,7 +952,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { // store/amo hits s3_valid := (s2_valid_masked && s2_hit || s2_replay) && !s2_sc_fail && isWrite(s2_req.cmd) - val amoalu = Module(new AMOALU) + val amoalu = Module(new AMOALU(xLen)) when ((s2_valid || s2_replay) && (isWrite(s2_req.cmd) || s2_data_correctable)) { s3_req := s2_req s3_req.data := Mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 119bd2b7..021f6cfa 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -20,13 +20,11 @@ case object UseUser extends Field[Boolean] case object UseDebug extends Field[Boolean] case object UseAtomics extends Field[Boolean] case object UseCompressed extends Field[Boolean] -case object UsePerfCounters extends Field[Boolean] case object FastLoadWord extends Field[Boolean] case object FastLoadByte extends Field[Boolean] case object MulUnroll extends Field[Int] case object DivEarlyOut extends Field[Boolean] case object CoreInstBits extends Field[Int] -case object CoreDataBits extends Field[Int] case object NCustomMRWCSRs extends Field[Int] case object MtvecWritable extends Field[Boolean] case object MtvecInit extends Field[BigInt] @@ -59,6 +57,14 @@ trait HasCoreParameters extends HasAddrMapParameters { val dcacheArbPorts = 1 + (if (usingVM) 1 else 0) + p(BuildRoCC).size val coreDCacheReqTagBits = 6 val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts) + + def pgIdxBits = 12 + def pgLevelBits = 10 - log2Ceil(xLen / 32) + def vaddrBits = pgIdxBits + pgLevels * pgLevelBits + def ppnBits = paddrBits - pgIdxBits + def vpnBits = vaddrBits - pgIdxBits + val pgLevels = p(PgLevels) + val asIdBits = p(ASIdBits) val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt val vaddrBitsExtended = vpnBitsExtended + pgIdxBits val coreMaxAddrBits = paddrBits max vaddrBitsExtended @@ -71,7 +77,6 @@ trait HasCoreParameters extends HasAddrMapParameters { // Print out log of committed instructions and their writeback values. // Requires post-processing due to out-of-order writebacks. val enableCommitLog = false - val usingPerfCounters = p(UsePerfCounters) val maxPAddrBits = xLen match { case 32 => 34 diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 5277c660..225ec447 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -11,6 +11,8 @@ import uncore.agents.PseudoLRU import uncore.coherence._ import uncore.util._ +case object PgLevels extends Field[Int] +case object ASIdBits extends Field[Int] case object NTLBEntries extends Field[Int] trait HasTLBParameters extends HasCoreParameters { diff --git a/uncore/src/main/scala/agents/Cache.scala b/uncore/src/main/scala/agents/Cache.scala index 262c2a8b..1c9e29e2 100644 --- a/uncore/src/main/scala/agents/Cache.scala +++ b/uncore/src/main/scala/agents/Cache.scala @@ -664,7 +664,7 @@ trait HasAMOALU extends HasAcquireMetadataBuffer // Provide a single ALU per tracker to merge Puts and AMOs with data being // refilled, written back, or extant in the cache - val amoalu = Module(new AMOALU(rhsIsAligned = true)) + val amoalu = Module(new AMOALU(amoAluOperandBits, rhsIsAligned = true)) val amo_result = Reg(init = UInt(0, innerDataBits)) def initializeAMOALUIOs() { diff --git a/uncore/src/main/scala/converters/Ahb.scala b/uncore/src/main/scala/converters/Ahb.scala index 0fca9517..c298e7b3 100644 --- a/uncore/src/main/scala/converters/Ahb.scala +++ b/uncore/src/main/scala/converters/Ahb.scala @@ -344,9 +344,8 @@ class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters) // Execute Atomic ops; unused and optimized away if !supportAtomics val amo_p = p.alterPartial({ case CacheBlockOffsetBits => hastiAddrBits - case AmoAluOperandBits => hastiDataBits }) - val alu = Module(new AMOALU(rhsIsAligned = true)(amo_p)) + val alu = Module(new AMOALU(hastiDataBits, rhsIsAligned = true)(amo_p)) alu.io.addr := haddr alu.io.cmd := cmd alu.io.typ := hsize diff --git a/uncore/src/main/scala/devices/Bram.scala b/uncore/src/main/scala/devices/Bram.scala index 9e360439..5bd24854 100644 --- a/uncore/src/main/scala/devices/Bram.scala +++ b/uncore/src/main/scala/devices/Bram.scala @@ -145,7 +145,7 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module data = Mux(r_acq.isAtomic(), r_old_data, ram(r_acq_addr))) val amo_shift_bits = acq.amo_shift_bytes() << UInt(3) - val amoalu = Module(new AMOALU(rhsIsAligned = true)) + val amoalu = Module(new AMOALU(amoAluOperandBits, rhsIsAligned = true)) amoalu.io.addr := Cat(acq.addr_block, acq.addr_beat, acq.addr_byte()) amoalu.io.cmd := acq.op_code() amoalu.io.typ := acq.op_size() diff --git a/uncore/src/main/scala/util/AmoAlu.scala b/uncore/src/main/scala/util/AmoAlu.scala index 965ddad1..40ae8d72 100644 --- a/uncore/src/main/scala/util/AmoAlu.scala +++ b/uncore/src/main/scala/util/AmoAlu.scala @@ -53,12 +53,10 @@ class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSiz def data = genData(0) } -class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Module { - val operandBits = p(AmoAluOperandBits) - val blockOffBits = p(CacheBlockOffsetBits) +class AMOALU(operandBits: Int, rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Module { require(operandBits == 32 || operandBits == 64) val io = new Bundle { - val addr = Bits(INPUT, blockOffBits) + val addr = Bits(INPUT, log2Ceil(operandBits/8)) val cmd = Bits(INPUT, M_SZ) val typ = Bits(INPUT, log2Ceil(log2Ceil(operandBits/8) + 1)) val lhs = Bits(INPUT, operandBits)