riscv/rocket-chip
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Remove parameters for some things that aren't parameterizable

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Heads up @colinschmidt and @ccelio.  I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them.  Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.
This commit is contained in:
Andrew Waterman
2016-08-16 20:04:02 -07:00
committed by Howard Mao
parent 33676e81f8
commit fee5d2b1ea
12 changed files with 22 additions and 43 deletions
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5
rocket/src/main/scala/nbdcache.scala
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@ -12,14 +12,13 @@ import uncore.constants._
import cde.{Parameters, Field}
import Util._
case object WordBits extends Field[Int]
case object StoreDataQueueDepth extends Field[Int]
case object ReplayQueueDepth extends Field[Int]
case object NMSHRs extends Field[Int]
case object LRSCCycles extends Field[Int]
trait HasL1HellaCacheParameters extends HasL1CacheParameters {
val wordBits = p(WordBits)
val wordBits = xLen // really, xLen max fLen
val wordBytes = wordBits/8
val wordOffBits = log2Up(wordBytes)
val beatBytes = p(CacheBlockBytes) / outerDataBeats
@ -953,7 +952,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
// store/amo hits
s3_valid := (s2_valid_masked && s2_hit || s2_replay) && !s2_sc_fail && isWrite(s2_req.cmd)
val amoalu = Module(new AMOALU)
val amoalu = Module(new AMOALU(xLen))
when ((s2_valid || s2_replay) && (isWrite(s2_req.cmd) || s2_data_correctable)) {
s3_req := s2_req
s3_req.data := Mux(s2_data_correctable, s2_data_corrected, amoalu.io.out)