Remove parameters for some things that aren't parameterizable

Heads up @colinschmidt and @ccelio.  I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them.  Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.

rocket/src/main/scala/dcache.scala

@@ -404,7 +404,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
 
   // AMOs
   if (usingAtomics) {
-    val amoalu = Module(new AMOALU)
+    val amoalu = Module(new AMOALU(xLen))
     amoalu.io.addr := pstore1_addr
     amoalu.io.cmd := pstore1_cmd
     amoalu.io.typ := pstore1_typ

rocket/src/main/scala/nbdcache.scala

@@ -12,14 +12,13 @@ import uncore.constants._
 import cde.{Parameters, Field}
 import Util._
 
-case object WordBits extends Field[Int]
 case object StoreDataQueueDepth extends Field[Int]
 case object ReplayQueueDepth extends Field[Int]
 case object NMSHRs extends Field[Int]
 case object LRSCCycles extends Field[Int]
 
 trait HasL1HellaCacheParameters extends HasL1CacheParameters {
-  val wordBits = p(WordBits)
+  val wordBits = xLen // really, xLen max fLen
   val wordBytes = wordBits/8
   val wordOffBits = log2Up(wordBytes)
   val beatBytes = p(CacheBlockBytes) / outerDataBeats
@@ -953,7 +952,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
 
   // store/amo hits
   s3_valid := (s2_valid_masked && s2_hit || s2_replay) && !s2_sc_fail && isWrite(s2_req.cmd)
-  val amoalu = Module(new AMOALU)
+  val amoalu = Module(new AMOALU(xLen))
   when ((s2_valid || s2_replay) && (isWrite(s2_req.cmd) || s2_data_correctable)) {
     s3_req := s2_req
     s3_req.data := Mux(s2_data_correctable, s2_data_corrected, amoalu.io.out)

rocket/src/main/scala/rocket.scala

@@ -20,13 +20,11 @@ case object UseUser extends Field[Boolean]
 case object UseDebug extends Field[Boolean]
 case object UseAtomics extends Field[Boolean]
 case object UseCompressed extends Field[Boolean]
-case object UsePerfCounters extends Field[Boolean]
 case object FastLoadWord extends Field[Boolean]
 case object FastLoadByte extends Field[Boolean]
 case object MulUnroll extends Field[Int]
 case object DivEarlyOut extends Field[Boolean]
 case object CoreInstBits extends Field[Int]
-case object CoreDataBits extends Field[Int]
 case object NCustomMRWCSRs extends Field[Int]
 case object MtvecWritable extends Field[Boolean]
 case object MtvecInit extends Field[BigInt]
@@ -59,6 +57,14 @@ trait HasCoreParameters extends HasAddrMapParameters {
   val dcacheArbPorts = 1 + (if (usingVM) 1 else 0) + p(BuildRoCC).size
   val coreDCacheReqTagBits = 6
   val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
+
+  def pgIdxBits = 12
+  def pgLevelBits = 10 - log2Ceil(xLen / 32)
+  def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
+  def ppnBits = paddrBits - pgIdxBits
+  def vpnBits = vaddrBits - pgIdxBits
+  val pgLevels = p(PgLevels)
+  val asIdBits = p(ASIdBits)
   val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
   val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
   val coreMaxAddrBits = paddrBits max vaddrBitsExtended
@@ -71,7 +77,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
   // Print out log of committed instructions and their writeback values.
   // Requires post-processing due to out-of-order writebacks.
   val enableCommitLog = false
-  val usingPerfCounters = p(UsePerfCounters)
 
   val maxPAddrBits = xLen match {
     case 32 => 34

rocket/src/main/scala/tlb.scala

@@ -11,6 +11,8 @@ import uncore.agents.PseudoLRU
 import uncore.coherence._
 import uncore.util._
 
+case object PgLevels extends Field[Int]
+case object ASIdBits extends Field[Int]
 case object NTLBEntries extends Field[Int]
 
 trait HasTLBParameters extends HasCoreParameters {