riscv/rocket-chip
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Significant changes and fixes to BTB for superscalar fetch.

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- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
This commit is contained in:
Christopher Celio
2014-11-11 03:34:05 -08:00
parent 3be3cd7731
commit fea31d2167
4 changed files with 63 additions and 45 deletions
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2
rocket/src/main/scala/dpath.scala
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@ -286,8 +286,8 @@ class Datapath extends Module
wb_reg_pc)).toUInt // PC_WB
io.imem.btb_update.bits.pc := mem_reg_pc
io.imem.btb_update.bits.target := io.imem.req.bits.pc
io.imem.btb_update.bits.returnAddr := mem_int_wdata
io.imem.btb_update.bits.br_pc := mem_reg_pc
io.imem.ras_update.bits.returnAddr := mem_int_wdata
// for hazard/bypass opportunity detection
io.ctrl.ex_waddr := ex_reg_inst(11,7)