riscv/rocket-chip
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Significant changes and fixes to BTB for superscalar fetch.

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- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
This commit is contained in:
Christopher Celio
2014-11-11 03:34:05 -08:00
parent 3be3cd7731
commit fea31d2167
4 changed files with 63 additions and 45 deletions
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11
rocket/src/main/scala/ctrl.scala
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@ -652,15 +652,18 @@ class Control extends Module
Mux(replay_wb, PC_WB, // replay
PC_MEM)))
io.imem.btb_update.valid := (mem_reg_branch || io.imem.btb_update.bits.isJump) && !take_pc_wb
io.imem.btb_update.valid := take_pc_mem && !take_pc_wb
io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
io.imem.btb_update.bits.taken := mem_reg_branch && io.dpath.mem_br_taken || io.imem.btb_update.bits.isJump
io.imem.btb_update.bits.mispredict := take_pc_mem
io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr
io.imem.btb_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0)
io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra
io.imem.req.valid := take_pc
io.imem.ras_update.valid := io.imem.btb_update.bits.isJump && !take_pc_wb
io.imem.ras_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0)
io.imem.ras_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra
io.imem.ras_update.bits.prediction.valid := mem_reg_btb_hit
io.imem.ras_update.bits.prediction.bits := mem_reg_btb_resp
io.imem.req.valid := take_pc
val bypassDst = Array(id_raddr1, id_raddr2)
val bypassSrc = Array.fill(NBYP)((Bool(true), UInt(0)))