From fc648d13a1248defb2dca4022d950b6fb5a631ed Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 11 Oct 2012 16:48:51 -0700 Subject: [PATCH] remove old Mux1H; add implicit conversions --- rocket/src/main/scala/dpath_util.scala | 25 ++++++++------------ rocket/src/main/scala/htif.scala | 12 ++++------ rocket/src/main/scala/nbdcache.scala | 32 +++++++++++++------------- rocket/src/main/scala/util.scala | 12 ++++------ 4 files changed, 34 insertions(+), 47 deletions(-) diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 61cec1fc..db1ef65d 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -28,34 +28,29 @@ class rocketDpathBTB(entries: Int) extends Component val hit = Bool() val update = Bool() var update_reduction = Bool(false) - val mux = (new Mux1H(entries)) { Bits(width = VADDR_BITS) } + val hits = Vec(entries) { Bool() } + val updates = Vec(entries) { Bool() } + val targets = Vec(entries) { Reg() { UFix() } } + val anyUpdate = updates.toBits.orR for (i <- 0 until entries) { val tag = Reg() { UFix() } - val target = Reg() { UFix() } val valid = Reg(resetVal = Bool(false)) - val my_hit = valid && tag === io.current_pc - val my_update = valid && tag === io.correct_pc + hits(i) := valid && tag === io.current_pc + updates(i) := valid && tag === io.correct_pc - when (io.wen && (my_update || !update && UFix(i) === repl_way)) { + when (io.wen && (updates(i) || !anyUpdate && UFix(i) === repl_way)) { valid := Bool(false) when (!io.clr) { valid := Bool(true) tag := io.correct_pc - target := io.correct_target + targets(i) := io.correct_target } } - - hit_reduction = hit_reduction || my_hit - update_reduction = update_reduction || my_update - mux.io.sel(i) := my_hit - mux.io.in(i) := target } - hit := hit_reduction - update := update_reduction - io.hit := hit - io.target := mux.io.out.toUFix + io.hit := hits.toBits.orR + io.target := Mux1H(hits, targets) } class ioDpathPCR extends Bundle() diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 335ef3cb..c6229b1a 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -189,11 +189,10 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C io.mem.probe_rep_data.valid := Bool(false) io.mem.incoherent := Bool(true) - val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) } + val pcrReadData = Vec(ncores) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } for (i <- 0 until ncores) { val my_reset = Reg(resetVal = Bool(true)) val my_ipi = Reg(resetVal = Bool(false)) - val rdata = Reg() { Bits() } val cpu = io.cpu(i) val me = pcr_coreid === UFix(i) @@ -221,25 +220,22 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C when (cmd === cmd_writecr) { my_reset := pcr_wdata(0) } - rdata := my_reset.toBits + pcrReadData(i) := my_reset.toBits state := state_tx } cpu.pcr_rep.ready := Bool(true) when (cpu.pcr_rep.valid) { - rdata := cpu.pcr_rep.bits + pcrReadData(i) := cpu.pcr_rep.bits state := state_tx } - - pcr_mux.io.sel(i) := me - pcr_mux.io.in(i) := rdata } val tx_cmd = Mux(nack, cmd_nack, cmd_ack) val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd) val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext) val tx_data = Mux(tx_word_count === UFix(0), tx_header, - Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcr_mux.io.out, + Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcrReadData(pcr_coreid), packet_ram(packet_ram_raddr))) io.host.in.ready := state === state_rx diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index a3402dcb..6c882b1c 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -325,9 +325,10 @@ class MSHRFile(co: CoherencePolicy) extends Component { val sdq = Mem(NSDQ) { io.req.bits.data.clone } when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data } - val tag_mux = (new Mux1H(NMSHR)){ Bits(width = TAG_BITS) } - val wb_probe_mux = (new Mux1H(NMSHR)) { new WritebackReq } - val mem_resp_mux = (new Mux1H(NMSHR)){ new DataArrayReq } + val idxMatch = Vec(NMSHR) { Bool() } + val tagList = Vec(NMSHR) { Bits() } + val wbTagList = Vec(NMSHR) { Bits() } + val memRespMux = Vec(NMSHR) { new DataArrayReq } val meta_req_arb = (new Arbiter(NMSHR)) { new MetaArrayReq() } val mem_req_arb = (new Arbiter(NMSHR)) { new TransactionInit } val mem_finish_arb = (new Arbiter(NMSHR)) { new TransactionFinish } @@ -335,8 +336,8 @@ class MSHRFile(co: CoherencePolicy) extends Component { val replay_arb = (new Arbiter(NMSHR)) { new Replay() } val alloc_arb = (new Arbiter(NMSHR)) { Bool() } - val tag_match = tag_mux.io.out === io.req.bits.tag - val wb_probe_match = wb_probe_mux.io.out.tag === io.req.bits.tag + val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.tag + val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.tag var idx_match = Bool(false) var pri_rdy = Bool(false) @@ -348,10 +349,9 @@ class MSHRFile(co: CoherencePolicy) extends Component { for (i <- 0 to NMSHR-1) { val mshr = new MSHR(i, co) - tag_mux.io.sel(i) := mshr.io.idx_match - tag_mux.io.in(i) := mshr.io.tag - wb_probe_mux.io.sel(i) := mshr.io.idx_match - wb_probe_mux.io.in(i) := mshr.io.wb_req.bits + idxMatch(i) := mshr.io.idx_match + tagList(i) := mshr.io.tag + wbTagList(i) := mshr.io.wb_req.bits.tag alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy mshr.io.req_pri_val := alloc_arb.io.in(i).ready @@ -371,10 +371,9 @@ class MSHRFile(co: CoherencePolicy) extends Component { mshr.io.mem_abort <> io.mem_abort mshr.io.mem_rep <> io.mem_rep - mem_resp_mux.io.sel(i) := UFix(i) === io.mem_rep.bits.tile_xact_id - mem_resp_mux.io.in(i).idx := mshr.io.idx - mem_resp_mux.io.in(i).offset := mshr.io.refill_count - mem_resp_mux.io.in(i).way_en := mshr.io.way_oh + memRespMux(i).idx := mshr.io.idx + memRespMux(i).offset := mshr.io.refill_count + memRespMux(i).way_en := mshr.io.way_oh pri_rdy = pri_rdy || mshr.io.req_pri_rdy sec_rdy = sec_rdy || mshr.io.req_sec_rdy @@ -393,9 +392,10 @@ class MSHRFile(co: CoherencePolicy) extends Component { io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy io.secondary_miss := idx_match - io.mem_resp_idx := mem_resp_mux.io.out.idx - io.mem_resp_offset := mem_resp_mux.io.out.offset - io.mem_resp_way_oh := mem_resp_mux.io.out.way_en + val memResp = memRespMux(io.mem_rep.bits.tile_xact_id) + io.mem_resp_idx := memResp.idx + io.mem_resp_offset := memResp.offset + io.mem_resp_way_oh := memResp.way_en io.fence_rdy := !fence io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match) diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 19856386..d5472420 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -4,13 +4,9 @@ import Chisel._ import Node._ import scala.math._ -class Mux1H [T <: Data](n: Int)(gen: => T) extends Component +object Util { - val io = new Bundle { - val sel = Vec(n) { Bool(dir = INPUT) } - val in = Vec(n) { gen }.asInput - val out = gen.asOutput - } - - io.out := Mux1H(io.sel, io.in) + implicit def intToUFix(x: Int): UFix = UFix(x) + implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false + implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 }