riscv/rocket-chip
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Handle invalidate_lr in cache arbiter, not tile

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This commit is contained in:
Andrew Waterman 2016-04-27 11:22:04 -07:00
parent b99db83e67
commit fb5c38c186
3 changed files with 2 additions and 1 deletions
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1
rocket/src/main/scala/arbiter.scala
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@ -16,6 +16,7 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
val r_valid = io.requestor.map(r => Reg(next=r.req.valid)) val r_valid = io.requestor.map(r => Reg(next=r.req.valid))
io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_)
io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
io.requestor(0).req.ready := io.mem.req.ready io.requestor(0).req.ready := io.mem.req.ready
for (i <- 1 until n) for (i <- 1 until n)

1
rocket/src/main/scala/ptw.scala
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@ -120,6 +120,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.mem.req.bits.addr := pte_addr io.mem.req.bits.addr := pte_addr
io.mem.s1_data := pte_wdata.toBits io.mem.s1_data := pte_wdata.toBits
io.mem.s1_kill := Bool(false) io.mem.s1_kill := Bool(false)
io.mem.invalidate_lr := Bool(false)
val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count) val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)

1
rocket/src/main/scala/tile.scala
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@ -47,7 +47,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem) val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]() val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem) val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
io.host <> core.io.host io.host <> core.io.host
icache.io.cpu <> core.io.imem icache.io.cpu <> core.io.imem