riscv/rocket-chip
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Handle invalidate_lr in cache arbiter, not tile

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This commit is contained in:
Andrew Waterman
2016-04-27 11:22:04 -07:00
parent b99db83e67
commit fb5c38c186
3 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/tile.scala
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@ -47,7 +47,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
io.host <> core.io.host
icache.io.cpu <> core.io.imem