riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

Handle invalidate_lr in cache arbiter, not tile

Browse Source
This commit is contained in:
Andrew Waterman committed 2016-04-27 11:22:04 -07:00
1 parent b99db83e67
commit fb5c38c186
3 files changed
+2 -1
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

rocket/src/main/scala/ptw.scala
+1
View File
@@ -120,6 +120,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.mem.req.bits.addr := pte_addr
io.mem.s1_data := pte_wdata.toBits
io.mem.s1_kill := Bool(false)
io.mem.invalidate_lr := Bool(false)
val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)