riscv/rocket-chip
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Handle invalidate_lr in cache arbiter, not tile

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This commit is contained in:
Andrew Waterman
2016-04-27 11:22:04 -07:00
parent b99db83e67
commit fb5c38c186
3 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/ptw.scala
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@ -120,6 +120,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.mem.req.bits.addr := pte_addr
io.mem.s1_data := pte_wdata.toBits
io.mem.s1_kill := Bool(false)
io.mem.invalidate_lr := Bool(false)
val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)