riscv/rocket-chip
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made setReadLatency argument a parameter defined in consts.scala

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This commit is contained in:
Rimas Avizienis 2011-12-05 00:33:17 -08:00
parent ff95cacb55
commit fa784d1d7d
3 changed files with 10 additions and 4 deletions
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2
rocket/src/main/scala/consts.scala
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@ -197,6 +197,8 @@ object Constants
val HAVE_RVC = Bool(false); val HAVE_RVC = Bool(false);
val HAVE_FPU = Bool(false); val HAVE_FPU = Bool(false);
val HAVE_VEC = Bool(false); val HAVE_VEC = Bool(false);
val SRAM_READ_LATENCY = 0;
} }
} }

6
rocket/src/main/scala/dcache.scala
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@ -250,7 +250,8 @@ class rocketDCacheDM(lines: Int) extends Component {
((state === s_resolve_miss) && r_req_flush); ((state === s_resolve_miss) && r_req_flush);
val tag_array = Mem4(lines, r_cpu_req_ppn); val tag_array = Mem4(lines, r_cpu_req_ppn);
tag_array.setReadLatency(0); tag_array.setReadLatency(SRAM_READ_LATENCY);
// tag_array.setTarget('inst);
val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we); val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
// valid bit array // valid bit array
@ -366,7 +367,8 @@ class rocketDCacheDM(lines: Int) extends Component {
store_wmask)); store_wmask));
val data_array = Mem4(lines*4, data_wdata); val data_array = Mem4(lines*4, data_wdata);
data_array.setReadLatency(0); data_array.setReadLatency(SRAM_READ_LATENCY);
// data_array.setTarget('inst);
val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask); val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask);
val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0)); val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
val r_resp_data = Reg(resp_data); val r_resp_data = Reg(resp_data);

6
rocket/src/main/scala/icache.scala
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@ -84,7 +84,8 @@ class rocketICacheDM(lines: Int) extends Component {
val tag_we = (state === s_refill_wait) && io.mem.resp_val; val tag_we = (state === s_refill_wait) && io.mem.resp_val;
val tag_array = Mem4(lines, r_cpu_req_ppn); val tag_array = Mem4(lines, r_cpu_req_ppn);
tag_array.setReadLatency(0); tag_array.setReadLatency(SRAM_READ_LATENCY);
// tag_array.setTarget('inst);
val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we); val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
// valid bit array // valid bit array
@ -104,7 +105,8 @@ class rocketICacheDM(lines: Int) extends Component {
Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count), Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix; io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
val data_array = Mem4(lines*4, io.mem.resp_data); val data_array = Mem4(lines*4, io.mem.resp_data);
data_array.setReadLatency(0); data_array.setReadLatency(SRAM_READ_LATENCY);
// data_array.setTarget('inst);
val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val); val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
// output signals // output signals