From fa784d1d7d852d483e7c483f4cc21d7b0056e262 Mon Sep 17 00:00:00 2001 From: Rimas Avizienis Date: Mon, 5 Dec 2011 00:33:17 -0800 Subject: [PATCH] made setReadLatency argument a parameter defined in consts.scala --- rocket/src/main/scala/consts.scala | 2 ++ rocket/src/main/scala/dcache.scala | 6 ++++-- rocket/src/main/scala/icache.scala | 6 ++++-- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 5a0ee148..d93eac51 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -197,6 +197,8 @@ object Constants val HAVE_RVC = Bool(false); val HAVE_FPU = Bool(false); val HAVE_VEC = Bool(false); + + val SRAM_READ_LATENCY = 0; } } diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index bd12811e..0c6849a2 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -250,7 +250,8 @@ class rocketDCacheDM(lines: Int) extends Component { ((state === s_resolve_miss) && r_req_flush); val tag_array = Mem4(lines, r_cpu_req_ppn); - tag_array.setReadLatency(0); + tag_array.setReadLatency(SRAM_READ_LATENCY); +// tag_array.setTarget('inst); val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we); // valid bit array @@ -366,7 +367,8 @@ class rocketDCacheDM(lines: Int) extends Component { store_wmask)); val data_array = Mem4(lines*4, data_wdata); - data_array.setReadLatency(0); + data_array.setReadLatency(SRAM_READ_LATENCY); +// data_array.setTarget('inst); val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask); val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0)); val r_resp_data = Reg(resp_data); diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 334fb616..c82dda68 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -84,7 +84,8 @@ class rocketICacheDM(lines: Int) extends Component { val tag_we = (state === s_refill_wait) && io.mem.resp_val; val tag_array = Mem4(lines, r_cpu_req_ppn); - tag_array.setReadLatency(0); + tag_array.setReadLatency(SRAM_READ_LATENCY); +// tag_array.setTarget('inst); val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we); // valid bit array @@ -104,7 +105,8 @@ class rocketICacheDM(lines: Int) extends Component { Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count), io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix; val data_array = Mem4(lines*4, io.mem.resp_data); - data_array.setReadLatency(0); + data_array.setReadLatency(SRAM_READ_LATENCY); +// data_array.setTarget('inst); val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val); // output signals