riscv/rocket-chip
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Fix RVC/uncacheable instruction memory performance bug

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9c1d126965 was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
This commit is contained in:
Andrew Waterman 2017-05-03 17:52:06 -07:00
parent 7b3d87a2e6
commit fa6ecdf813
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/Frontend.scala
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@ -158,7 +158,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay
icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt
icache.io.s2_kill := RegNext(RegNext(s0_valid)) && s2_speculative && !s2_cacheable || s2_xcpt
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
fq.io.enq.bits.pc := s2_pc