From fa6ecdf813d18b23dc175a9e056a53329db653db Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 3 May 2017 17:52:06 -0700 Subject: [PATCH] Fix RVC/uncacheable instruction memory performance bug 9c1d12696552c70313c0c0ba22fef49287187d88 was an incomplete fix, so sometimes we were requesting pipeline replays when they weren't necessary. --- src/main/scala/rocket/Frontend.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index c2f69fd7..c906b21e 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -158,7 +158,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay - icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt + icache.io.s2_kill := RegNext(RegNext(s0_valid)) && s2_speculative && !s2_cacheable || s2_xcpt fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill) fq.io.enq.bits.pc := s2_pc