changes to match junctions no-mmio-base

uncore/src/main/scala/interconnect.scala

@@ -291,7 +291,7 @@ class TileLinkRecursiveInterconnect(
   addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach {
     case (((entry, (start, size)), xbarOut), i) => {
       entry.region match {
-        case MemSize(_, _) =>
+        case MemSize(_, _, _) =>
           io.out(outInd) <> xbarOut
           outInd += 1
         case MemSubmap(_, submap) =>

uncore/src/main/scala/scr.scala

@@ -1,7 +1,7 @@
 package uncore
 
 import Chisel._
-import junctions.{SmiIO, MMIOBase}
+import junctions.SmiIO
 import cde.Parameters
 import scala.collection.mutable.HashMap
 import scala.collection.mutable.ArrayBuffer