From f9de99ed40547dfc34336549e41681e08e9742f1 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 21 Apr 2016 15:35:37 -0700
Subject: [PATCH] changes to match junctions no-mmio-base

---
 uncore/src/main/scala/interconnect.scala | 2 +-
 uncore/src/main/scala/scr.scala          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/uncore/src/main/scala/interconnect.scala b/uncore/src/main/scala/interconnect.scala
index c9ad3f1e..428474ba 100644
--- a/uncore/src/main/scala/interconnect.scala
+++ b/uncore/src/main/scala/interconnect.scala
@@ -291,7 +291,7 @@ class TileLinkRecursiveInterconnect(
   addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach {
     case (((entry, (start, size)), xbarOut), i) => {
       entry.region match {
-        case MemSize(_, _) =>
+        case MemSize(_, _, _) =>
           io.out(outInd) <> xbarOut
           outInd += 1
         case MemSubmap(_, submap) =>
diff --git a/uncore/src/main/scala/scr.scala b/uncore/src/main/scala/scr.scala
index 9f1ed7d1..f076364d 100644
--- a/uncore/src/main/scala/scr.scala
+++ b/uncore/src/main/scala/scr.scala
@@ -1,7 +1,7 @@
 package uncore
 
 import Chisel._
-import junctions.{SmiIO, MMIOBase}
+import junctions.SmiIO
 import cde.Parameters
 import scala.collection.mutable.HashMap
 import scala.collection.mutable.ArrayBuffer