riscv/rocket-chip
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changes to match junctions no-mmio-base

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Howard Mao
2016-04-21 15:35:37 -07:00
parent 9b3faff5a5
commit f9de99ed40
2 changed files with 2 additions and 2 deletions
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2
uncore/src/main/scala/interconnect.scala
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@@ -291,7 +291,7 @@ class TileLinkRecursiveInterconnect(
addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach { addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach {
case (((entry, (start, size)), xbarOut), i) => { case (((entry, (start, size)), xbarOut), i) => {
entry.region match { entry.region match {
case MemSize(_, _) => case MemSize(_, _, _) =>
io.out(outInd) <> xbarOut io.out(outInd) <> xbarOut
outInd += 1 outInd += 1
case MemSubmap(_, submap) => case MemSubmap(_, submap) =>

2
uncore/src/main/scala/scr.scala
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@@ -1,7 +1,7 @@
package uncore package uncore
import Chisel._ import Chisel._
import junctions.{SmiIO, MMIOBase} import junctions.SmiIO
import cde.Parameters import cde.Parameters
import scala.collection.mutable.HashMap import scala.collection.mutable.HashMap
import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.ArrayBuffer