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tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp

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This commit is contained in:
Wesley W. Terpstra 2016-08-31 10:25:46 -07:00
parent 5b31fb81fe
commit f99a3dbec7
6 changed files with 23 additions and 29 deletions
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22
uncore/src/main/scala/tilelink2/Bases.scala
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@ -6,7 +6,7 @@ import Chisel._
import scala.collection.mutable.ListBuffer
import chisel3.internal.sourceinfo.SourceInfo
abstract class TLFactory
abstract class LazyModule
{
private val bindings = ListBuffer[(TLBaseNode, Int, TLBaseNode, Int, SourceInfo)]()
@ -15,17 +15,17 @@ abstract class TLFactory
bindings += ((manager, i, client, j, sourceInfo))
}
def module: TLModule
def module: LazyModuleImp
protected[tilelink2] def instantiate() = {
// Find all TLFactory members of self
// Find all LazyModule members of self
for (m <- getClass.getMethods) {
if (m.getParameterTypes.isEmpty &&
!java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
!(m.getName contains '$') &&
classOf[TLFactory].isAssignableFrom(m.getReturnType)) {
classOf[LazyModule].isAssignableFrom(m.getReturnType)) {
// ... and force their lazy module members to exist
m.invoke(this).asInstanceOf[TLFactory].module
m.invoke(this).asInstanceOf[LazyModule].module
}
}
bindings.foreach { case (x, i, y, j, s) =>
@ -41,14 +41,8 @@ abstract class TLFactory
}
}
// Use this if you have only one node => makes factory adapters possible
abstract class TLSimpleFactory extends TLFactory
abstract class LazyModuleImp(outer: LazyModule) extends Module
{
def node: TLBaseNode
}
abstract class TLModule(factory: TLFactory) extends Module
{
override def desiredName = factory.getClass.getName.split('.').last
factory.instantiate()
override def desiredName = outer.getClass.getName.split('.').last
outer.instantiate()
}

4
uncore/src/main/scala/tilelink2/HintHandler.scala
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@ -5,13 +5,13 @@ package uncore.tilelink2
import Chisel._
// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends TLSimpleFactory
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { case Seq(c) => if (supportClients) c.copy(clients = c.clients .map(_.copy(supportsHint = true))) else c },
managerFn = { case Seq(m) => if (supportManagers) m.copy(managers = m.managers.map(_.copy(supportsHint = true))) else m })
lazy val module = Module(new TLModule(this) {
lazy val module = Module(new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut

4
uncore/src/main/scala/tilelink2/Legacy.scala
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@ -7,14 +7,14 @@ import cde.Parameters
import uncore.tilelink._
import uncore.constants._
class TLLegacy(implicit val p: Parameters) extends TLSimpleFactory with HasTileLinkParameters
class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkParameters
{
val outer_p = p
// TL legacy clients don't support anything fancy
val node = TLClientNode(TLClientParameters(
sourceId = IdRange(0, 1 << tlClientXactIdBits)))
lazy val module = Module(new TLModule(this) with HasTileLinkParameters {
lazy val module = Module(new LazyModuleImp(this) with HasTileLinkParameters {
val p = outer_p
val io = new Bundle {
val legacy = new ClientUncachedTileLinkIO()(p).flip

14
uncore/src/main/scala/tilelink2/RegisterRouter.scala
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@ -59,25 +59,25 @@ object TLRegisterNode
// register mapped device from a totally abstract register mapped device.
// See GPIO.scala in this directory for an example
abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLSimpleFactory
abstract class TLRegisterRouterBase(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends LazyModule
{
val node = TLRegisterNode(address, concurrency, beatBytes)
}
class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory)
extends TLModule(factory) with HasRegMap
class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
{
val io = bundleBuilder
def regmap(mapping: RegField.Map*) = factory.node.regmap(mapping:_*)
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
}
class TLRegisterRouter[B <: Bundle, M <: TLModule]
class TLRegisterRouter[B <: Bundle, M <: LazyModuleImp]
(address: Option[BigInt] = None, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
(bundleBuilder: Vec[TLBundle] => B)
(moduleBuilder: (=> B, TLRegFactory) => M)
extends TLRegFactory(AddressSet(size-1, address), concurrency, beatBytes)
(moduleBuilder: (=> B, TLRegisterRouterBase) => M)
extends TLRegisterRouterBase(AddressSet(size-1, address), concurrency, beatBytes)
{
require (size % 4096 == 0) // devices should be 4K aligned
require (isPow2(size))

4
uncore/src/main/scala/tilelink2/SRAM.scala
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@ -4,7 +4,7 @@ package uncore.tilelink2
import Chisel._
class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(address),
@ -17,7 +17,7 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
// We require the address range to include an entire beat (for the write mask)
require ((address.mask & (beatBytes-1)) == beatBytes-1)
lazy val module = Module(new TLModule(this) {
lazy val module = Module(new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
}

4
uncore/src/main/scala/tilelink2/Xbar.scala
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@ -13,7 +13,7 @@ object TLXbar
}
}
class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLSimpleFactory
class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends LazyModule
{
def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
@ -65,7 +65,7 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
TLManagerPortParameters(managers, seq(0).beatBytes)
})
lazy val module = Module(new TLModule(this) {
lazy val module = Module(new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut