Add performance counter support
This commit is contained in:
Andrew Waterman
parent
1e3339e97c
commit
f91552a650
@ -1 +1 @@
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Subproject commit 745e74afb56ecba090669615d4ac9c9b9b96c653
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Subproject commit 95332642272844a5aa0a20a47d725b00b3ae388a
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@ -112,6 +112,8 @@ class BaseCoreplexConfig extends Config (
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case UseUser => true
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case UseDebug => true
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case NBreakpoints => 1
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case NPerfCounters => 0
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case NPerfEvents => 0
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case FastLoadWord => true
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case FastLoadByte => false
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case XLen => 64
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@ -4,6 +4,7 @@ package rocket
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import Chisel._
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import Util._
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import uncore.util._
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import Instructions._
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import cde.{Parameters, Field}
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import uncore.devices._
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@ -106,6 +107,14 @@ object CSR
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require(debugIntCause >= Causes.all.max)
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debugIntCause
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}
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val firstCtr = CSRs.cycle
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val firstHPM = 3
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val firstHPC = CSRs.cycle + firstHPM
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val firstHPE = CSRs.mucounteren + firstHPM
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val firstMHPC = CSRs.mcycle + firstHPM
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val nHPM = 29
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val nCtr = firstHPM + nHPM
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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@ -139,6 +148,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val interrupt = Bool(OUTPUT)
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val interrupt_cause = UInt(OUTPUT, xLen)
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val bp = Vec(nBreakpoints, new BP).asOutput
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val events = Vec(nPerfEvents, Bool()).asInput
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}
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class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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@ -197,15 +207,18 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints)))
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val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
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val reg_mie = Reg(init=UInt(0, xLen))
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val reg_mideleg = Reg(init=UInt(0, xLen))
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val reg_medeleg = Reg(init=UInt(0, xLen))
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val reg_mie = Reg(UInt(width = xLen))
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val reg_mideleg = Reg(UInt(width = xLen))
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val reg_medeleg = Reg(UInt(width = xLen))
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val reg_mip = Reg(new MIP)
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val reg_mepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_mcause = Reg(Bits(width = xLen))
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val reg_mbadaddr = Reg(UInt(width = vaddrBitsExtended))
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val reg_mscratch = Reg(Bits(width = xLen))
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val reg_mtvec = Reg(init=UInt(p(MtvecInit), paddrBits min xLen))
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val reg_mucounteren = Reg(UInt(width = 32))
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val reg_mscounteren = Reg(UInt(width = 32))
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val delegable_counters = (BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1
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val reg_sepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_scause = Reg(Bits(width = xLen))
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@ -219,7 +232,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val reg_frm = Reg(UInt(width = 3))
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val reg_instret = WideCounter(64, io.retire)
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val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(64) }
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val reg_cycle = if (enableCommitLog) reg_instret else WideCounter(64)
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val reg_hpmevent = Seq.fill(nPerfCounters)(if (nPerfEvents > 1) Reg(UInt(width = log2Ceil(nPerfEvents))) else UInt(0))
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val reg_hpmcounter = reg_hpmevent.map(e => WideCounter(64, ((UInt(0) +: io.events): Seq[UInt])(e)))
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val mip = Wire(init=reg_mip)
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mip.rocc := io.rocc.interrupt
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@ -243,6 +258,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val system_insn = io.rw.cmd === CSR.I
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val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R
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val isa_string = "IM" +
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(if (usingVM) "S" else "") +
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@ -263,10 +279,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.mvendorid -> UInt(0),
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CSRs.mcycle -> reg_cycle,
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CSRs.minstret -> reg_instret,
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CSRs.mucounteren -> UInt(0),
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CSRs.mutime_delta -> UInt(0),
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CSRs.mucycle_delta -> UInt(0),
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CSRs.muinstret_delta -> UInt(0),
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CSRs.misa -> UInt(isa),
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CSRs.mstatus -> read_mstatus,
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CSRs.mtvec -> reg_mtvec,
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@ -280,19 +292,27 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.mcause -> reg_mcause,
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CSRs.mhartid -> io.prci.id)
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val debug_csrs = collection.mutable.LinkedHashMap[Int,Bits](
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val debug_csrs = collection.immutable.ListMap(
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CSRs.dcsr -> reg_dcsr.asUInt,
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CSRs.dpc -> reg_dpc.asUInt,
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CSRs.dscratch -> reg_dscratch.asUInt
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)
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CSRs.dscratch -> reg_dscratch.asUInt)
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val fp_csrs = collection.immutable.ListMap(
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CSRs.fflags -> reg_fflags,
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CSRs.frm -> reg_frm,
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CSRs.fcsr -> Cat(reg_frm, reg_fflags))
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if (usingDebug)
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read_mapping ++= debug_csrs
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if (usingFPU) {
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read_mapping += CSRs.fflags -> reg_fflags
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read_mapping += CSRs.frm -> reg_frm
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read_mapping += CSRs.fcsr -> Cat(reg_frm, reg_fflags)
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if (usingFPU)
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read_mapping ++= fp_csrs
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for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, UInt(0))
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zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, UInt(0))) zipWithIndex) {
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read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
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read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN
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if (usingUser) read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN
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}
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if (usingVM) {
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@ -317,22 +337,21 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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read_mapping += CSRs.sptbr -> reg_sptbr.asUInt
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read_mapping += CSRs.sepc -> reg_sepc.sextTo(xLen)
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read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
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read_mapping += CSRs.mscounteren -> UInt(0)
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read_mapping += CSRs.mstime_delta -> UInt(0)
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read_mapping += CSRs.mscycle_delta -> UInt(0)
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read_mapping += CSRs.msinstret_delta -> UInt(0)
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read_mapping += CSRs.mscounteren -> reg_mscounteren
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}
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if (usingUser) {
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read_mapping += CSRs.mucounteren -> reg_mucounteren
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read_mapping += CSRs.cycle -> reg_cycle
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read_mapping += CSRs.instret -> reg_instret
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}
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if (xLen == 32) {
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read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
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read_mapping += CSRs.minstreth -> (reg_instret >> 32)
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read_mapping += CSRs.mutime_deltah -> UInt(0)
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read_mapping += CSRs.mucycle_deltah -> UInt(0)
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read_mapping += CSRs.muinstret_deltah -> UInt(0)
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if (usingVM) {
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read_mapping += CSRs.mstime_deltah -> UInt(0)
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read_mapping += CSRs.mscycle_deltah -> UInt(0)
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read_mapping += CSRs.msinstret_deltah -> UInt(0)
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if (usingUser) {
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read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
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read_mapping += CSRs.instreth -> (reg_instret >> 32)
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}
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}
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@ -345,9 +364,11 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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val fp_csr =
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if (usingFPU) decoded_addr(CSRs.fflags) || decoded_addr(CSRs.frm) || decoded_addr(CSRs.fcsr)
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else Bool(false)
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val fp_csr = if (usingFPU) decoded_addr.filterKeys(fp_csrs contains _ ).values reduce(_||_) else Bool(false)
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val hpm_csr = if (usingUser) io.rw.addr >= CSR.firstCtr && io.rw.addr < CSR.firstCtr + CSR.nCtr else Bool(false)
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val hpm_en = reg_debug || reg_mstatus.prv === PRV.M ||
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(reg_mstatus.prv === PRV.S && reg_mscounteren(io.rw.addr(log2Ceil(CSR.nCtr)-1, 0))) ||
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(reg_mstatus.prv === PRV.U && reg_mucounteren(io.rw.addr(log2Ceil(CSR.nCtr)-1, 0)))
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val csr_addr_priv = io.rw.addr(9,8)
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val debug_csr_mask = 0x090 // only debug CSRs have address bits 7 and 4 set
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@ -356,8 +377,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val csr_debug = Bool(usingDebug) && (io.rw.addr & debug_csr_mask) === debug_csr_mask
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val priv_sufficient = reg_debug || (!csr_debug && reg_mstatus.prv >= csr_addr_priv)
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val read_only = io.rw.addr(11,10).andR
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
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val wen = cpu_wen && !read_only
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val wen = cpu_wen && priv_sufficient && !read_only
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val wdata = (Mux(io.rw.cmd.isOneOf(CSR.S, CSR.C), io.rw.rdata, UInt(0)) |
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Mux(io.rw.cmd =/= CSR.C, io.rw.wdata, UInt(0))) &
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@ -372,7 +392,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val insn_wfi = do_system_insn && opcode(5)
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io.csr_xcpt := (cpu_wen && read_only) ||
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(cpu_ren && (!priv_sufficient || !addr_valid || fp_csr && !io.status.fs.orR)) ||
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(cpu_ren && (!priv_sufficient || !addr_valid || (hpm_csr && !hpm_en) || (fp_csr && !io.status.fs.orR))) ||
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(system_insn && !priv_sufficient) ||
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insn_call || insn_break
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@ -506,6 +526,15 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata >> 2 << 2 }
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when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
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when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
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for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter) zipWithIndex) {
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writeCounter(i + CSR.firstMHPC, c, wdata)
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if (nPerfEvents > 1)
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when (decoded_addr(i + CSR.firstHPE)) { e := wdata }
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}
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writeCounter(CSRs.mcycle, reg_cycle, wdata)
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writeCounter(CSRs.minstret, reg_instret, wdata)
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if (usingFPU) {
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when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
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when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
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@ -547,6 +576,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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when (decoded_addr(CSRs.sbadaddr)) { reg_sbadaddr := wdata(vaddrBitsExtended-1,0) }
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when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata & delegable_interrupts }
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when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata & delegable_exceptions }
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when (decoded_addr(CSRs.mscounteren)) { reg_mscounteren := wdata & delegable_counters }
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}
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if (usingUser) {
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when (decoded_addr(CSRs.mucounteren)) { reg_mucounteren := wdata & delegable_counters }
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}
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if (nBreakpoints > 0) {
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when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
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@ -600,4 +633,14 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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def trimPrivilege(priv: UInt): UInt =
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if (usingVM) priv
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else legalizePrivilege(priv)
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def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {
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if (xLen == 32) {
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val hi = lo + CSRs.mcycleh - CSRs.mcycle
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when (decoded_addr(lo)) { ctr := Cat(ctr(63, 32), wdata) }
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when (decoded_addr(hi)) { ctr := Cat(wdata, ctr(31, 0)) }
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} else {
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when (decoded_addr(lo)) { ctr := wdata }
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}
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}
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}
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@ -250,6 +250,35 @@ object CSRs {
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val cycle = 0xc00
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val time = 0xc01
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val instret = 0xc02
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val hpmcounter3 = 0xc03
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val hpmcounter4 = 0xc04
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val hpmcounter5 = 0xc05
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val hpmcounter6 = 0xc06
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val hpmcounter7 = 0xc07
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val hpmcounter8 = 0xc08
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val hpmcounter9 = 0xc09
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val hpmcounter10 = 0xc0a
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val hpmcounter11 = 0xc0b
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val hpmcounter12 = 0xc0c
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val hpmcounter13 = 0xc0d
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val hpmcounter14 = 0xc0e
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val hpmcounter15 = 0xc0f
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val hpmcounter16 = 0xc10
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val hpmcounter17 = 0xc11
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val hpmcounter18 = 0xc12
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val hpmcounter19 = 0xc13
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val hpmcounter20 = 0xc14
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val hpmcounter21 = 0xc15
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val hpmcounter22 = 0xc16
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val hpmcounter23 = 0xc17
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val hpmcounter24 = 0xc18
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val hpmcounter25 = 0xc19
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val hpmcounter26 = 0xc1a
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val hpmcounter27 = 0xc1b
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val hpmcounter28 = 0xc1c
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val hpmcounter29 = 0xc1d
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val hpmcounter30 = 0xc1e
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val hpmcounter31 = 0xc1f
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val sstatus = 0x100
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val sie = 0x104
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val stvec = 0x105
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@ -259,10 +288,8 @@ object CSRs {
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val sbadaddr = 0x143
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val sip = 0x144
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val sptbr = 0x180
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val scycle = 0xd00
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val stime = 0xd01
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val sinstret = 0xd02
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val mstatus = 0x300
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val misa = 0x301
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val medeleg = 0x302
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val mideleg = 0x303
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val mie = 0x304
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@ -272,14 +299,6 @@ object CSRs {
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val mcause = 0x342
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val mbadaddr = 0x343
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val mip = 0x344
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val mucounteren = 0x310
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val mscounteren = 0x311
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val mucycle_delta = 0x700
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val mutime_delta = 0x701
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val muinstret_delta = 0x702
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val mscycle_delta = 0x704
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val mstime_delta = 0x705
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val msinstret_delta = 0x706
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val tselect = 0x7a0
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val tdata1 = 0x7a1
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val tdata2 = 0x7a2
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@ -287,27 +306,135 @@ object CSRs {
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val dcsr = 0x7b0
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val dpc = 0x7b1
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val dscratch = 0x7b2
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val mcycle = 0xf00
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val mtime = 0xf01
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val minstret = 0xf02
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val misa = 0xf10
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val mcycle = 0xb00
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val minstret = 0xb02
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val mhpmcounter3 = 0xb03
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val mhpmcounter4 = 0xb04
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val mhpmcounter5 = 0xb05
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val mhpmcounter6 = 0xb06
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val mhpmcounter7 = 0xb07
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val mhpmcounter8 = 0xb08
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val mhpmcounter9 = 0xb09
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val mhpmcounter10 = 0xb0a
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val mhpmcounter11 = 0xb0b
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val mhpmcounter12 = 0xb0c
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val mhpmcounter13 = 0xb0d
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val mhpmcounter14 = 0xb0e
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val mhpmcounter15 = 0xb0f
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val mhpmcounter16 = 0xb10
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val mhpmcounter17 = 0xb11
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val mhpmcounter18 = 0xb12
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val mhpmcounter19 = 0xb13
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val mhpmcounter20 = 0xb14
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val mhpmcounter21 = 0xb15
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val mhpmcounter22 = 0xb16
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val mhpmcounter23 = 0xb17
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val mhpmcounter24 = 0xb18
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val mhpmcounter25 = 0xb19
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val mhpmcounter26 = 0xb1a
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val mhpmcounter27 = 0xb1b
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val mhpmcounter28 = 0xb1c
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val mhpmcounter29 = 0xb1d
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val mhpmcounter30 = 0xb1e
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val mhpmcounter31 = 0xb1f
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val mucounteren = 0x320
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val mscounteren = 0x321
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val mhpmevent3 = 0x323
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val mhpmevent4 = 0x324
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val mhpmevent5 = 0x325
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val mhpmevent6 = 0x326
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val mhpmevent7 = 0x327
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val mhpmevent8 = 0x328
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val mhpmevent9 = 0x329
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val mhpmevent10 = 0x32a
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val mhpmevent11 = 0x32b
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val mhpmevent12 = 0x32c
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val mhpmevent13 = 0x32d
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val mhpmevent14 = 0x32e
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val mhpmevent15 = 0x32f
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val mhpmevent16 = 0x330
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val mhpmevent17 = 0x331
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val mhpmevent18 = 0x332
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val mhpmevent19 = 0x333
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val mhpmevent20 = 0x334
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val mhpmevent21 = 0x335
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val mhpmevent22 = 0x336
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val mhpmevent23 = 0x337
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val mhpmevent24 = 0x338
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val mhpmevent25 = 0x339
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val mhpmevent26 = 0x33a
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val mhpmevent27 = 0x33b
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val mhpmevent28 = 0x33c
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val mhpmevent29 = 0x33d
|
||||
val mhpmevent30 = 0x33e
|
||||
val mhpmevent31 = 0x33f
|
||||
val mvendorid = 0xf11
|
||||
val marchid = 0xf12
|
||||
val mimpid = 0xf13
|
||||
val mhartid = 0xf14
|
||||
val mreset = 0x7c2
|
||||
val cycleh = 0xc80
|
||||
val timeh = 0xc81
|
||||
val instreth = 0xc82
|
||||
val mucycle_deltah = 0x780
|
||||
val mutime_deltah = 0x781
|
||||
val muinstret_deltah = 0x782
|
||||
val mscycle_deltah = 0x784
|
||||
val mstime_deltah = 0x785
|
||||
val msinstret_deltah = 0x786
|
||||
val mcycleh = 0xf80
|
||||
val mtimeh = 0xf81
|
||||
val minstreth = 0xf82
|
||||
val hpmcounter3h = 0xc83
|
||||
val hpmcounter4h = 0xc84
|
||||
val hpmcounter5h = 0xc85
|
||||
val hpmcounter6h = 0xc86
|
||||
val hpmcounter7h = 0xc87
|
||||
val hpmcounter8h = 0xc88
|
||||
val hpmcounter9h = 0xc89
|
||||
val hpmcounter10h = 0xc8a
|
||||
val hpmcounter11h = 0xc8b
|
||||
val hpmcounter12h = 0xc8c
|
||||
val hpmcounter13h = 0xc8d
|
||||
val hpmcounter14h = 0xc8e
|
||||
val hpmcounter15h = 0xc8f
|
||||
val hpmcounter16h = 0xc90
|
||||
val hpmcounter17h = 0xc91
|
||||
val hpmcounter18h = 0xc92
|
||||
val hpmcounter19h = 0xc93
|
||||
val hpmcounter20h = 0xc94
|
||||
val hpmcounter21h = 0xc95
|
||||
val hpmcounter22h = 0xc96
|
||||
val hpmcounter23h = 0xc97
|
||||
val hpmcounter24h = 0xc98
|
||||
val hpmcounter25h = 0xc99
|
||||
val hpmcounter26h = 0xc9a
|
||||
val hpmcounter27h = 0xc9b
|
||||
val hpmcounter28h = 0xc9c
|
||||
val hpmcounter29h = 0xc9d
|
||||
val hpmcounter30h = 0xc9e
|
||||
val hpmcounter31h = 0xc9f
|
||||
val mcycleh = 0xb80
|
||||
val minstreth = 0xb82
|
||||
val mhpmcounter3h = 0xb83
|
||||
val mhpmcounter4h = 0xb84
|
||||
val mhpmcounter5h = 0xb85
|
||||
val mhpmcounter6h = 0xb86
|
||||
val mhpmcounter7h = 0xb87
|
||||
val mhpmcounter8h = 0xb88
|
||||
val mhpmcounter9h = 0xb89
|
||||
val mhpmcounter10h = 0xb8a
|
||||
val mhpmcounter11h = 0xb8b
|
||||
val mhpmcounter12h = 0xb8c
|
||||
val mhpmcounter13h = 0xb8d
|
||||
val mhpmcounter14h = 0xb8e
|
||||
val mhpmcounter15h = 0xb8f
|
||||
val mhpmcounter16h = 0xb90
|
||||
val mhpmcounter17h = 0xb91
|
||||
val mhpmcounter18h = 0xb92
|
||||
val mhpmcounter19h = 0xb93
|
||||
val mhpmcounter20h = 0xb94
|
||||
val mhpmcounter21h = 0xb95
|
||||
val mhpmcounter22h = 0xb96
|
||||
val mhpmcounter23h = 0xb97
|
||||
val mhpmcounter24h = 0xb98
|
||||
val mhpmcounter25h = 0xb99
|
||||
val mhpmcounter26h = 0xb9a
|
||||
val mhpmcounter27h = 0xb9b
|
||||
val mhpmcounter28h = 0xb9c
|
||||
val mhpmcounter29h = 0xb9d
|
||||
val mhpmcounter30h = 0xb9e
|
||||
val mhpmcounter31h = 0xb9f
|
||||
val all = {
|
||||
val res = collection.mutable.ArrayBuffer[Int]()
|
||||
res += fflags
|
||||
@ -316,6 +443,35 @@ object CSRs {
|
||||
res += cycle
|
||||
res += time
|
||||
res += instret
|
||||
res += hpmcounter3
|
||||
res += hpmcounter4
|
||||
res += hpmcounter5
|
||||
res += hpmcounter6
|
||||
res += hpmcounter7
|
||||
res += hpmcounter8
|
||||
res += hpmcounter9
|
||||
res += hpmcounter10
|
||||
res += hpmcounter11
|
||||
res += hpmcounter12
|
||||
res += hpmcounter13
|
||||
res += hpmcounter14
|
||||
res += hpmcounter15
|
||||
res += hpmcounter16
|
||||
res += hpmcounter17
|
||||
res += hpmcounter18
|
||||
res += hpmcounter19
|
||||
res += hpmcounter20
|
||||
res += hpmcounter21
|
||||
res += hpmcounter22
|
||||
res += hpmcounter23
|
||||
res += hpmcounter24
|
||||
res += hpmcounter25
|
||||
res += hpmcounter26
|
||||
res += hpmcounter27
|
||||
res += hpmcounter28
|
||||
res += hpmcounter29
|
||||
res += hpmcounter30
|
||||
res += hpmcounter31
|
||||
res += sstatus
|
||||
res += sie
|
||||
res += stvec
|
||||
@ -325,10 +481,8 @@ object CSRs {
|
||||
res += sbadaddr
|
||||
res += sip
|
||||
res += sptbr
|
||||
res += scycle
|
||||
res += stime
|
||||
res += sinstret
|
||||
res += mstatus
|
||||
res += misa
|
||||
res += medeleg
|
||||
res += mideleg
|
||||
res += mie
|
||||
@ -338,14 +492,6 @@ object CSRs {
|
||||
res += mcause
|
||||
res += mbadaddr
|
||||
res += mip
|
||||
res += mucounteren
|
||||
res += mscounteren
|
||||
res += mucycle_delta
|
||||
res += mutime_delta
|
||||
res += muinstret_delta
|
||||
res += mscycle_delta
|
||||
res += mstime_delta
|
||||
res += msinstret_delta
|
||||
res += tselect
|
||||
res += tdata1
|
||||
res += tdata2
|
||||
@ -354,14 +500,71 @@ object CSRs {
|
||||
res += dpc
|
||||
res += dscratch
|
||||
res += mcycle
|
||||
res += mtime
|
||||
res += minstret
|
||||
res += misa
|
||||
res += mhpmcounter3
|
||||
res += mhpmcounter4
|
||||
res += mhpmcounter5
|
||||
res += mhpmcounter6
|
||||
res += mhpmcounter7
|
||||
res += mhpmcounter8
|
||||
res += mhpmcounter9
|
||||
res += mhpmcounter10
|
||||
res += mhpmcounter11
|
||||
res += mhpmcounter12
|
||||
res += mhpmcounter13
|
||||
res += mhpmcounter14
|
||||
res += mhpmcounter15
|
||||
res += mhpmcounter16
|
||||
res += mhpmcounter17
|
||||
res += mhpmcounter18
|
||||
res += mhpmcounter19
|
||||
res += mhpmcounter20
|
||||
res += mhpmcounter21
|
||||
res += mhpmcounter22
|
||||
res += mhpmcounter23
|
||||
res += mhpmcounter24
|
||||
res += mhpmcounter25
|
||||
res += mhpmcounter26
|
||||
res += mhpmcounter27
|
||||
res += mhpmcounter28
|
||||
res += mhpmcounter29
|
||||
res += mhpmcounter30
|
||||
res += mhpmcounter31
|
||||
res += mucounteren
|
||||
res += mscounteren
|
||||
res += mhpmevent3
|
||||
res += mhpmevent4
|
||||
res += mhpmevent5
|
||||
res += mhpmevent6
|
||||
res += mhpmevent7
|
||||
res += mhpmevent8
|
||||
res += mhpmevent9
|
||||
res += mhpmevent10
|
||||
res += mhpmevent11
|
||||
res += mhpmevent12
|
||||
res += mhpmevent13
|
||||
res += mhpmevent14
|
||||
res += mhpmevent15
|
||||
res += mhpmevent16
|
||||
res += mhpmevent17
|
||||
res += mhpmevent18
|
||||
res += mhpmevent19
|
||||
res += mhpmevent20
|
||||
res += mhpmevent21
|
||||
res += mhpmevent22
|
||||
res += mhpmevent23
|
||||
res += mhpmevent24
|
||||
res += mhpmevent25
|
||||
res += mhpmevent26
|
||||
res += mhpmevent27
|
||||
res += mhpmevent28
|
||||
res += mhpmevent29
|
||||
res += mhpmevent30
|
||||
res += mhpmevent31
|
||||
res += mvendorid
|
||||
res += marchid
|
||||
res += mimpid
|
||||
res += mhartid
|
||||
res += mreset
|
||||
res.toArray
|
||||
}
|
||||
val all32 = {
|
||||
@ -369,15 +572,66 @@ object CSRs {
|
||||
res += cycleh
|
||||
res += timeh
|
||||
res += instreth
|
||||
res += mucycle_deltah
|
||||
res += mutime_deltah
|
||||
res += muinstret_deltah
|
||||
res += mscycle_deltah
|
||||
res += mstime_deltah
|
||||
res += msinstret_deltah
|
||||
res += hpmcounter3h
|
||||
res += hpmcounter4h
|
||||
res += hpmcounter5h
|
||||
res += hpmcounter6h
|
||||
res += hpmcounter7h
|
||||
res += hpmcounter8h
|
||||
res += hpmcounter9h
|
||||
res += hpmcounter10h
|
||||
res += hpmcounter11h
|
||||
res += hpmcounter12h
|
||||
res += hpmcounter13h
|
||||
res += hpmcounter14h
|
||||
res += hpmcounter15h
|
||||
res += hpmcounter16h
|
||||
res += hpmcounter17h
|
||||
res += hpmcounter18h
|
||||
res += hpmcounter19h
|
||||
res += hpmcounter20h
|
||||
res += hpmcounter21h
|
||||
res += hpmcounter22h
|
||||
res += hpmcounter23h
|
||||
res += hpmcounter24h
|
||||
res += hpmcounter25h
|
||||
res += hpmcounter26h
|
||||
res += hpmcounter27h
|
||||
res += hpmcounter28h
|
||||
res += hpmcounter29h
|
||||
res += hpmcounter30h
|
||||
res += hpmcounter31h
|
||||
res += mcycleh
|
||||
res += mtimeh
|
||||
res += minstreth
|
||||
res += mhpmcounter3h
|
||||
res += mhpmcounter4h
|
||||
res += mhpmcounter5h
|
||||
res += mhpmcounter6h
|
||||
res += mhpmcounter7h
|
||||
res += mhpmcounter8h
|
||||
res += mhpmcounter9h
|
||||
res += mhpmcounter10h
|
||||
res += mhpmcounter11h
|
||||
res += mhpmcounter12h
|
||||
res += mhpmcounter13h
|
||||
res += mhpmcounter14h
|
||||
res += mhpmcounter15h
|
||||
res += mhpmcounter16h
|
||||
res += mhpmcounter17h
|
||||
res += mhpmcounter18h
|
||||
res += mhpmcounter19h
|
||||
res += mhpmcounter20h
|
||||
res += mhpmcounter21h
|
||||
res += mhpmcounter22h
|
||||
res += mhpmcounter23h
|
||||
res += mhpmcounter24h
|
||||
res += mhpmcounter25h
|
||||
res += mhpmcounter26h
|
||||
res += mhpmcounter27h
|
||||
res += mhpmcounter28h
|
||||
res += mhpmcounter29h
|
||||
res += mhpmcounter30h
|
||||
res += mhpmcounter31h
|
||||
res.toArray
|
||||
}
|
||||
}
|
||||
|
||||
@ -28,6 +28,8 @@ case object MtvecWritable extends Field[Boolean]
|
||||
case object MtvecInit extends Field[BigInt]
|
||||
case object ResetVector extends Field[BigInt]
|
||||
case object NBreakpoints extends Field[Int]
|
||||
case object NPerfCounters extends Field[Int]
|
||||
case object NPerfEvents extends Field[Int]
|
||||
|
||||
trait HasCoreParameters extends HasAddrMapParameters {
|
||||
implicit val p: Parameters
|
||||
@ -44,6 +46,8 @@ trait HasCoreParameters extends HasAddrMapParameters {
|
||||
val fastLoadWord = p(FastLoadWord)
|
||||
val fastLoadByte = p(FastLoadByte)
|
||||
val nBreakpoints = p(NBreakpoints)
|
||||
val nPerfCounters = p(NPerfCounters)
|
||||
val nPerfEvents = p(NPerfEvents)
|
||||
|
||||
val retireWidth = p(RetireWidth)
|
||||
val fetchWidth = p(FetchWidth)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user