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MetaData & friends moved to uncore/

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This commit is contained in:
Henry Cook 2014-04-23 16:24:20 -07:00
parent 39681303b8
commit f8f29c69b8
1 changed files with 10 additions and 10 deletions
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20
uncore/src/main/scala/cache.scala
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@ -74,34 +74,34 @@ class RandomReplacement(implicit val conf: CacheConfig) extends ReplacementPolic
def hit = {} def hit = {}
} }
object L2MetaData { object MetaData {
def apply(tag: Bits, state: UInt)(implicit conf: CacheConfig) = { def apply(tag: Bits, state: UInt)(implicit conf: CacheConfig) = {
val meta = new L2MetaData val meta = new MetaData
meta.state := state meta.state := state
meta.tag := tag meta.tag := tag
meta meta
} }
} }
class L2MetaData(implicit val conf: CacheConfig) extends CacheBundle { class MetaData(implicit val conf: CacheConfig) extends CacheBundle {
val state = UInt(width = conf.statebits) val state = UInt(width = conf.statebits)
val tag = Bits(width = conf.tagbits) val tag = Bits(width = conf.tagbits)
} }
class L2MetaReadReq(implicit val conf: CacheConfig) extends CacheBundle { class MetaReadReq(implicit val conf: CacheConfig) extends CacheBundle {
val idx = Bits(width = conf.idxbits) val idx = Bits(width = conf.idxbits)
} }
class L2MetaWriteReq(implicit conf: CacheConfig) extends L2MetaReadReq()(conf) { class MetaWriteReq(implicit conf: CacheConfig) extends MetaReadReq()(conf) {
val way_en = Bits(width = conf.ways) val way_en = Bits(width = conf.ways)
val data = new L2MetaData() val data = new MetaData()
} }
class L2MetaDataArray(implicit conf: CacheConfig) extends Module { class MetaDataArray(implicit conf: CacheConfig) extends Module {
implicit val tl = conf.tl implicit val tl = conf.tl
val io = new Bundle { val io = new Bundle {
val read = Decoupled(new L2MetaReadReq).flip val read = Decoupled(new MetaReadReq).flip
val write = Decoupled(new L2MetaWriteReq).flip val write = Decoupled(new MetaWriteReq).flip
val resp = Vec.fill(conf.ways){(new L2MetaData).asOutput} val resp = Vec.fill(conf.ways){(new MetaData).asOutput}
} }
val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1))) val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1)))