riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB

Browse Source
This commit is contained in:
Rimas Avizienis
2011-11-10 11:26:13 -08:00
parent 4bd0263a4a
commit f86d5b1334
9 changed files with 119 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/util.scala
View File

@ -29,7 +29,7 @@ class priorityDecoder(width: Int) extends Component
class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle
{
val in = Bits(in_width, 'input);
val in = Bits(in_width, 'input);
val out = UFix(out_width, 'output);
}