riscv/rocket-chip
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB

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Rimas Avizienis committed 2011-11-10 11:26:13 -08:00
1 parent 4bd0263a4a
commit f86d5b1334
9 files changed
+119 -109
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rocket/src/main/scala/util.scala
+1 -1
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@@ -29,7 +29,7 @@ class priorityDecoder(width: Int) extends Component
class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle
{
val in = Bits(in_width, 'input);
val in = Bits(in_width, 'input);
val out = UFix(out_width, 'output);
}