diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 800de56d..9d7d4484 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -146,15 +146,19 @@ object Constants val PCR_COUNT = UFix( 4, 5); val PCR_COMPARE = UFix( 5, 5); val PCR_CAUSE = UFix( 6, 5); + val PCR_IPI = UFix( 7, 5); val PCR_MEMSIZE = UFix( 8, 5); val PCR_PTBR = UFix( 9, 5); - val PCR_LOG = UFix(10, 5); + val PCR_COREID = UFix(10, 5); + val PCR_NUMCORES = UFix(12, 5); val PCR_TOHOST = UFix(16, 5); val PCR_FROMHOST = UFix(17, 5); val PCR_CONSOLE = UFix(18, 5); val PCR_K0 = UFix(24, 5); val PCR_K1 = UFix(25, 5); + val COREID = 0; + val NUMCORES = 1; val PADDR_BITS = 40; val VADDR_BITS = 43; val PGIDX_BITS = 13; diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 0c2d2e0f..2f58276f 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -7,7 +7,6 @@ import Constants._; class ioDebug(view: List[String] = null) extends Bundle(view) { val error_mode = Bool('output); - val log_control = Bool('output); val id_valid = Bool('output); val ex_valid = Bool('output); val mem_valid = Bool('output); diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index 644a73b3..068ccc6a 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -17,7 +17,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) { val resp_miss = Bool('output); val resp_val = Bool('output); val resp_data = Bits(64, 'output); - val resp_tag = Bits(13, 'output); + val resp_tag = Bits(12, 'output); } // interface between D$ and next level in memory hierarchy diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index a8b0a528..6d611217 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -11,7 +11,7 @@ class ioDpathDmem extends Bundle() val req_tag = UFix(5, 'output); val req_data = Bits(64, 'output); val resp_val = Bool('input); - val resp_tag = Bits(13, 'input); // FIXME: MSB is ignored + val resp_tag = Bits(12, 'input); // FIXME: MSB is ignored val resp_data = Bits(64, 'input); } @@ -35,7 +35,8 @@ class rocketDpath extends Component { val io = new ioDpathAll(); - val btb = new rocketDpathBTB(); + val btb = new rocketDpathBTB(8); // # of entries in BTB + val if_btb_target = btb.io.target; val pcr = new rocketDpathPCR(); @@ -357,7 +358,6 @@ class rocketDpath extends Component io.ctrl.status := pcr.io.status; io.ptbr := pcr.io.ptbr; io.debug.error_mode := pcr.io.debug.error_mode; - io.debug.log_control := pcr.io.debug.log_control; // branch resolution logic io.ctrl.br_eq := (ex_reg_rs1 === ex_reg_rs2); diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index fc2de9bf..2ef560d0 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -4,6 +4,7 @@ package Top import Chisel._; import Node._; import Constants._; +import scala.math._; class ioDpathBTB extends Bundle() { @@ -15,17 +16,34 @@ class ioDpathBTB extends Bundle() val correct_target = UFix(VADDR_BITS, 'input); } -class rocketDpathBTB extends Component +// basic direct-mapped branch target buffer +class rocketDpathBTB(entries: Int) extends Component { - override val io = new ioDpathBTB(); - val rst_lwlr_pf = Mem(4, io.wen, io.correct_pc4(3, 2), UFix(1, 1), resetVal = UFix(0, 1)); - val lwlr_pf = Mem(4, io.wen, io.correct_pc4(3, 2), - Cat(io.correct_pc4(VADDR_BITS-1,4), io.correct_target(VADDR_BITS-1,2)), resetVal = UFix(0, 1)); - val is_val = rst_lwlr_pf(io.current_pc4(3, 2)); - val tag_target = lwlr_pf(io.current_pc4(3, 2)); + val io = new ioDpathBTB(); - io.hit := (is_val & (tag_target(2*VADDR_BITS-7,VADDR_BITS-2) === io.current_pc4(VADDR_BITS-1, 4))).toBool; - io.target := Cat(tag_target(VADDR_BITS-3, 0), Bits(0,2)).toUFix; + val addr_bits = ceil(log10(entries)/log10(2)).toInt; + val idxlsb = 2; + val idxmsb = idxlsb+addr_bits-1; + val tagmsb = (VADDR_BITS-idxmsb-1)+(VADDR_BITS-idxlsb)-1; + val taglsb = (VADDR_BITS-idxlsb); + + val rst_lwlr_pf = Mem(entries, io.wen, io.correct_pc4(idxmsb,idxlsb), UFix(1,1), resetVal = UFix(0,1)); + val lwlr_pf = Mem(entries, io.wen, io.correct_pc4(idxmsb,idxlsb), + Cat(io.correct_pc4(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)), resetVal = UFix(0,1)); + val is_val = rst_lwlr_pf(io.current_pc4(idxmsb,idxlsb)); + val tag_target = lwlr_pf(io.current_pc4(idxmsb, idxlsb)); + + io.hit := (is_val & (tag_target(tagmsb,taglsb) === io.current_pc4(VADDR_BITS-1, idxmsb+1))).toBool; + io.target := Cat(tag_target(taglsb-1, 0), Bits(0,idxlsb)).toUFix; + +// val rst_lwlr_pf = Mem(entries, io.wen, io.correct_pc4(3, 2), UFix(1, 1), resetVal = UFix(0, 1)); +// val lwlr_pf = Mem(entries, io.wen, io.correct_pc4(3, 2), +// Cat(io.correct_pc4(VADDR_BITS-1,4), io.correct_target(VADDR_BITS-1,2)), resetVal = UFix(0, 1)); +// val is_val = rst_lwlr_pf(io.current_pc4(3, 2)); +// val tag_target = lwlr_pf(io.current_pc4(3, 2)); +// +// io.hit := (is_val & (tag_target(2*VADDR_BITS-7,VADDR_BITS-2) === io.current_pc4(VADDR_BITS-1, 4))).toBool; +// io.target := Cat(tag_target(VADDR_BITS-3, 0), Bits(0,2)).toUFix; } class ioDpathPCR extends Bundle() @@ -49,22 +67,20 @@ class ioDpathPCR extends Bundle() class rocketDpathPCR extends Component { val io = new ioDpathPCR(); - val w = 32; val reg_epc = Reg(resetVal = UFix(0, VADDR_BITS)); val reg_badvaddr = Reg(resetVal = UFix(0, VADDR_BITS)); val reg_ebase = Reg(resetVal = UFix(0, VADDR_BITS)); - val reg_count = Reg(resetVal = Bits(0, w)); - val reg_compare = Reg(resetVal = Bits(0, w)); + val reg_count = Reg(resetVal = Bits(0, 32)); + val reg_compare = Reg(resetVal = Bits(0, 32)); val reg_cause = Reg(resetVal = Bits(0, 5)); - val reg_tohost = Reg(resetVal = Bits(0, w)); - val reg_fromhost = Reg(resetVal = Bits(0, w)); - val reg_k0 = Reg(resetVal = Bits(0, 2*w)); - val reg_k1 = Reg(resetVal = Bits(0, 2*w)); + val reg_tohost = Reg(resetVal = Bits(0, 32)); + val reg_fromhost = Reg(resetVal = Bits(0, 32)); + val reg_k0 = Reg(resetVal = Bits(0, 64)); + val reg_k1 = Reg(resetVal = Bits(0, 64)); val reg_ptbr = Reg(resetVal = UFix(0, PADDR_BITS)); val reg_error_mode = Reg(resetVal = Bool(false)); - val reg_log_control = Reg(resetVal = Bool(false)); val reg_status_vm = Reg(resetVal = Bool(false)); val reg_status_im = Reg(resetVal = Bits(0,8)); val reg_status_sx = Reg(resetVal = Bool(true)); @@ -81,19 +97,18 @@ class rocketDpathPCR extends Component io.status := Cat(reg_status_vm, reg_status_im, reg_status); io.evec := reg_ebase; io.ptbr := reg_ptbr; - io.host.to := Mux(io.host.from_wen, Bits(0, w), reg_tohost); + io.host.to := Mux(io.host.from_wen, Bits(0,32), reg_tohost); io.debug.error_mode := reg_error_mode; - io.debug.log_control := reg_log_control; io.r.data := rdata; when (io.host.from_wen) { - reg_tohost <== Bits(0, w); + reg_tohost <== Bits(0,32); reg_fromhost <== io.host.from; } otherwise { when (!io.exception && io.w.en && (io.w.addr === PCR_TOHOST)) { - reg_tohost <== io.w.data(w-1, 0); - reg_fromhost <== Bits(0, w); + reg_tohost <== io.w.data(31,0); + reg_fromhost <== Bits(0,32); } } @@ -133,33 +148,33 @@ class rocketDpathPCR extends Component when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS-1,0).toUFix; } when (io.w.addr === PCR_BADVADDR) { reg_badvaddr <== io.w.data(VADDR_BITS-1,0).toUFix; } when (io.w.addr === PCR_EVEC) { reg_ebase <== io.w.data(VADDR_BITS-1,0).toUFix; } - when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(w-1,0); } - when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(w-1,0); } + when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(31,0); } + when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(31,0); } when (io.w.addr === PCR_CAUSE) { reg_cause <== io.w.data(4,0); } - when (io.w.addr === PCR_LOG) { reg_log_control <== io.w.data(0).toBool; } - when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data(w-1,0); } + when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data(31,0); } when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; } when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; } when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } } - when (!io.r.en) { rdata <== Bits(0,2*w); } + when (!io.r.en) { rdata <== Bits(0,64); } switch (io.r.addr) { - is (PCR_STATUS) { rdata <== Cat(Bits(0,w+15), reg_status_vm, reg_status_im, reg_status); } - is (PCR_EPC) { rdata <== Cat(Fill(2*w-VADDR_BITS, reg_epc(VADDR_BITS-1)), reg_epc); } - is (PCR_BADVADDR) { rdata <== Cat(Fill(2*w-VADDR_BITS, reg_badvaddr(VADDR_BITS-1)), reg_badvaddr); } - is (PCR_EVEC) { rdata <== Cat(Fill(2*w-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); } - is (PCR_COUNT) { rdata <== Cat(Fill(w, reg_count(w-1)), reg_count); } - is (PCR_COMPARE) { rdata <== Cat(Fill(w, reg_compare(w-1)), reg_compare); } - is (PCR_CAUSE) { rdata <== Cat(Bits(0,w+27), reg_cause); } - is (PCR_MEMSIZE) { rdata <== Bits(MEMSIZE_PAGES, 64); } - is (PCR_LOG) { rdata <== Cat(Bits(0,63), reg_log_control); } - is (PCR_FROMHOST) { rdata <== Cat(Fill(w, reg_fromhost(w-1)), reg_fromhost); } - is (PCR_TOHOST) { rdata <== Cat(Fill(w, reg_tohost(w-1)), reg_tohost); } + is (PCR_STATUS) { rdata <== Cat(Bits(0,47), reg_status_vm, reg_status_im, reg_status); } + is (PCR_EPC) { rdata <== Cat(Fill(64-VADDR_BITS, reg_epc(VADDR_BITS-1)), reg_epc); } + is (PCR_BADVADDR) { rdata <== Cat(Fill(64-VADDR_BITS, reg_badvaddr(VADDR_BITS-1)), reg_badvaddr); } + is (PCR_EVEC) { rdata <== Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); } + is (PCR_COUNT) { rdata <== Cat(Fill(32, reg_count(31)), reg_count); } + is (PCR_COMPARE) { rdata <== Cat(Fill(32, reg_compare(31)), reg_compare); } + is (PCR_CAUSE) { rdata <== Cat(Bits(0,59), reg_cause); } + is (PCR_MEMSIZE) { rdata <== Bits(MEMSIZE_PAGES,64); } + is (PCR_COREID) { rdata <== Bits(COREID,64); } + is (PCR_NUMCORES) { rdata <== Bits(NUMCORES,64); } + is (PCR_FROMHOST) { rdata <== Cat(Fill(32, reg_fromhost(31)), reg_fromhost); } + is (PCR_TOHOST) { rdata <== Cat(Fill(32, reg_tohost(31)), reg_tohost); } is (PCR_K0) { rdata <== reg_k0; } is (PCR_K1) { rdata <== reg_k1; } - is (PCR_PTBR) { rdata <== Cat(Bits(0,2*w-PADDR_BITS), reg_ptbr); } - otherwise { rdata <== Bits(0,2*w); } + is (PCR_PTBR) { rdata <== Cat(Bits(0,64-PADDR_BITS), reg_ptbr); } + otherwise { rdata <== Bits(0,64); } } } diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala index 557a7e24..d27ffdc8 100644 --- a/rocket/src/main/scala/dtlb.scala +++ b/rocket/src/main/scala/dtlb.scala @@ -56,6 +56,7 @@ class rocketDTLB(entries: Int) extends Component val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn); + tag_cam.io.clear := io.cpu.invalidate; tag_cam.io.tag := lookup_tag; tag_cam.io.write := io.ptw.resp_val; tag_cam.io.write_tag := r_refill_tag; @@ -72,15 +73,6 @@ class rocketDTLB(entries: Int) extends Component val ptw_perm_sr = io.ptw.resp_perm(4); val ptw_perm_sw = io.ptw.resp_perm(5); - // valid bit array - val vb_array = Reg(resetVal = Bits(0, entries)); - when (io.cpu.invalidate) { - vb_array <== Bits(0, entries); - } - when (io.ptw.resp_val) { - vb_array <== vb_array.bitSet(r_refill_waddr, Bool(true)); - } - // permission bit arrays val ur_array = Reg(resetVal = Bits(0, entries)); // user execute permission val uw_array = Reg(resetVal = Bits(0, entries)); // user execute permission @@ -103,15 +95,15 @@ class rocketDTLB(entries: Int) extends Component } // high if there are any unused (invalid) entries in the TLB - val invalid_entry = ~vb_array.toUFix.orR(); + val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries)); val ie_enc = new priorityEncoder(entries); - ie_enc.io.in := vb_array.toUFix; + ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix; val ie_addr = ie_enc.io.out; val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix; - val tag_hit = tag_cam.io.hit && vb_array(tag_hit_addr).toBool; - val lookup_miss = (state === s_ready) && status_vm && io.cpu.req_val && !tag_hit; + val tag_hit = io.cpu.req_val && tag_cam.io.hit; + val lookup_miss = (state === s_ready) && status_vm && !tag_hit; when (lookup_miss) { r_refill_tag <== lookup_tag; @@ -123,13 +115,13 @@ class rocketDTLB(entries: Int) extends Component io.cpu.xcpt_ld := status_vm && tag_hit && req_load && - ((status_mode && !sw_array(tag_hit_addr).toBool) || - (!status_mode && !uw_array(tag_hit_addr).toBool)); + !((status_mode && sw_array(tag_hit_addr).toBool) || + (!status_mode && uw_array(tag_hit_addr).toBool)); io.cpu.xcpt_st := status_vm && tag_hit && req_store && - ((status_mode && !sr_array(tag_hit_addr).toBool) || - (!status_mode && !ur_array(tag_hit_addr).toBool)); + !((status_mode && sr_array(tag_hit_addr).toBool) || + (!status_mode && ur_array(tag_hit_addr).toBool)); io.cpu.req_rdy := (state === s_ready); io.cpu.resp_miss := lookup_miss; diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala index 9337392c..55620a28 100644 --- a/rocket/src/main/scala/itlb.scala +++ b/rocket/src/main/scala/itlb.scala @@ -6,10 +6,12 @@ import Node._; import Constants._; import scala.math._; -class ioCAM(addr_bits: Int, tag_bits: Int) extends Bundle { +class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle { + val clear = Bool('input); val tag = Bits(tag_bits, 'input); val hit = Bool('output); val hit_addr = UFix(addr_bits, 'output); + val valid_bits = Bits(entries, 'output); val write = Bool('input); val write_tag = Bits(tag_bits, 'input); @@ -17,24 +19,33 @@ class ioCAM(addr_bits: Int, tag_bits: Int) extends Bundle { } class rocketCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Component { - val io = new ioCAM(addr_bits, tag_bits); - val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag); + val io = new ioCAM(entries, addr_bits, tag_bits); + val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag); - val l_hit = Wire() { Bool() }; - val l_hit_addr = Wire() { UFix() }; + val l_hit = Wire() { Bool() }; + val l_hit_addr = Wire() { UFix() }; - for (i <- 0 to entries-1) { - when (cam_tags(UFix(i)) === io.tag) { - l_hit <== Bool(true); - l_hit_addr <== UFix(i,addr_bits); - } - } + val vb_array = Reg(resetVal = Bits(0, entries)); + when (io.clear) { + vb_array <== Bits(0, entries); + } + when (io.write) { + vb_array <== vb_array.bitSet(io.write_addr, Bool(true)); + } - l_hit <== Bool(false); - l_hit_addr <== UFix(0, addr_bits); - - io.hit := l_hit; - io.hit_addr := l_hit_addr; + for (i <- 0 to entries-1) { + when (vb_array(UFix(i)).toBool && (cam_tags(UFix(i)) === io.tag)) { + l_hit <== Bool(true); + l_hit_addr <== UFix(i,addr_bits); + } + } + + l_hit <== Bool(false); + l_hit_addr <== UFix(0, addr_bits); + + io.valid_bits := vb_array; + io.hit := l_hit; + io.hit_addr := l_hit_addr; } // interface between TLB and PTW @@ -94,6 +105,7 @@ class rocketITLB(entries: Int) extends Component val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn); + tag_cam.io.clear := io.cpu.invalidate; tag_cam.io.tag := lookup_tag; tag_cam.io.write := io.ptw.resp_val; tag_cam.io.write_tag := r_refill_tag; @@ -108,15 +120,6 @@ class rocketITLB(entries: Int) extends Component val ptw_perm_ux = io.ptw.resp_perm(0); val ptw_perm_sx = io.ptw.resp_perm(3); - // valid bit array - val vb_array = Reg(resetVal = Bits(0, entries)); - when (io.cpu.invalidate) { - vb_array <== Bits(0, entries); - } - when (io.ptw.resp_val) { - vb_array <== vb_array.bitSet(r_refill_waddr, Bool(true)); - } - // permission bit arrays val ux_array = Reg(resetVal = Bits(0, entries)); // user execute permission val sx_array = Reg(resetVal = Bits(0, entries)); // supervisor execute permission @@ -132,17 +135,16 @@ class rocketITLB(entries: Int) extends Component sx_array <== sx_array.bitSet(r_refill_waddr, Bool(false)); } - // high if there are any unused (invalid) entries in the ITLB -// val invalid_entry = orR(~vb_array); - val invalid_entry = ~vb_array.toUFix.orR(); + // high if there are any unused entries in the ITLB + val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries)); val ie_enc = new priorityEncoder(entries); - ie_enc.io.in := vb_array.toUFix; + ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix; val ie_addr = ie_enc.io.out; val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix; - val tag_hit = tag_cam.io.hit && vb_array(tag_hit_addr).toBool; - val lookup_miss = (state === s_ready) && status_vm && io.cpu.req_val && !tag_hit; + val tag_hit = io.cpu.req_val && tag_cam.io.hit; + val lookup_miss = (state === s_ready) && status_vm && !tag_hit; when (lookup_miss) { r_refill_tag <== lookup_tag; @@ -153,10 +155,9 @@ class rocketITLB(entries: Int) extends Component } val itlb_exception = - io.cpu.req_val && tag_hit && - ((status_mode && !sx_array(tag_hit_addr).toBool) || - (!status_mode && !ux_array(tag_hit_addr).toBool) || - (io.cpu.resp_addr >= MEMSIZE)); + tag_hit && + !((status_mode && sx_array(tag_hit_addr).toBool) || + (!status_mode && ux_array(tag_hit_addr).toBool)); io.cpu.req_rdy := (state === s_ready); io.cpu.resp_val := Mux(status_vm, tag_hit, io.cpu.req_val); @@ -171,7 +172,7 @@ class rocketITLB(entries: Int) extends Component // control state machine switch (state) { is (s_ready) { - when (status_vm && io.cpu.req_val && !tag_hit) { + when (status_vm && !tag_hit) { state <== s_request; } } diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 596f3e43..524984e5 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -27,14 +27,13 @@ class rocketDmemArbiter extends Component io.cpu.req_rdy := io.mem.req_rdy && !io.ptw.req_val; io.cpu.resp_miss := io.mem.resp_miss; // FIXME - io.cpu.resp_val := io.mem.resp_val && !io.mem.resp_tag(12).toBool; - io.ptw.resp_val := io.mem.resp_val && io.mem.resp_tag(12).toBool; + io.cpu.resp_val := io.mem.resp_val && !io.mem.resp_tag(11).toBool; + io.ptw.resp_val := io.mem.resp_val && io.mem.resp_tag(11).toBool; io.ptw.resp_data := io.mem.resp_data; io.cpu.resp_data := io.mem.resp_data; -// io.cpu.resp_tag := io.mem.resp_tag(11,0); - io.cpu.resp_tag := io.mem.resp_tag; // to get rid of warning, MSB of tag is ignored in dpath - +// io.cpu.resp_tag := io.mem.resp_tag(10,0); + io.cpu.resp_tag := io.mem.resp_tag; } class ioPTW extends Bundle @@ -55,7 +54,7 @@ class rocketPTW extends Component val r_req_vpn = Reg(resetVal = Bits(0,VPN_BITS)); val r_req_dest = Reg(resetVal = Bool(false)); // 0 = ITLB, 1 = DTLB - val req_addr = Reg(resetVal = UFix(0,PPN_BITS+PGIDX_BITS)); + val req_addr = Reg(resetVal = UFix(0,PADDR_BITS)); val r_resp_ppn = Reg(resetVal = Bits(0,PPN_BITS)); val r_resp_perm = Reg(resetVal = Bits(0,PERM_BITS)); @@ -69,17 +68,17 @@ class rocketPTW extends Component when ((state === s_ready) && req_itlb_val) { r_req_vpn <== io.itlb.req_vpn; r_req_dest <== Bool(false); - req_addr <== Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.itlb.req_vpn(VPN_BITS-1,VPN_BITS-10)).toUFix; + req_addr <== Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.itlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix; } when ((state === s_ready) && req_dtlb_val) { r_req_vpn <== io.dtlb.req_vpn; r_req_dest <== Bool(true); - req_addr <== Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.dtlb.req_vpn(VPN_BITS-1,VPN_BITS-10)).toUFix; + req_addr <== Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.dtlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix; } when (io.dmem.resp_val) { - req_addr <== Cat(io.dmem.resp_data(PADDR_BITS-1, PGIDX_BITS), vpn_idx).toUFix; + req_addr <== Cat(io.dmem.resp_data(PADDR_BITS-1, PGIDX_BITS), vpn_idx, Bits(0,3)).toUFix; r_resp_perm <== io.dmem.resp_data(9,4); r_resp_ppn <== io.dmem.resp_data(PADDR_BITS-1, PGIDX_BITS); } diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 9c60d726..edc3173d 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -29,7 +29,7 @@ class priorityDecoder(width: Int) extends Component class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle { - val in = Bits(in_width, 'input); + val in = Bits(in_width, 'input); val out = UFix(out_width, 'output); }