riscv/rocket-chip
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB

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Rimas Avizienis
2011-11-10 11:26:13 -08:00
parent 4bd0263a4a
commit f86d5b1334
9 changed files with 119 additions and 109 deletions
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rocket/src/main/scala/dcache.scala
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@ -17,7 +17,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
val resp_miss = Bool('output);
val resp_val = Bool('output);
val resp_data = Bits(64, 'output);
val resp_tag = Bits(13, 'output);
val resp_tag = Bits(12, 'output);
}
// interface between D$ and next level in memory hierarchy